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DWC2 Register Encoding + FIFO/PHY + Split-Transaction Support

June 24, 2026 · Sigil-Docs · sigil-drivers d57fcfe
driversusbdwc2pi0.7.0

Spec-correct Synopsys DWC2 register field encoding — the fix that unlocks hub enumeration and split-transaction support for the Pi 3B keyboard behind the LAN9514 hub.

Fixes

HCCHAR encoding
DevAddr<<22, EPNum<<11, EPDir<<15, EPType<<18, MPS in bits 0-10 — correct field packing per Synopsys spec.
HCTSIZ encoding
XferSize bits 0-18, PktCnt bits 19-28, Pid bits 29-30 — correct transfer size register layout.
DMA bus alias
0xC000_0000|arm_phys — Pi 3B DMA core view address translation for GPU-side DMA.
FIFO sizing
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ — correct FIFO allocation for RX, non-periodic TX, and periodic TX.
PHY config
GUSBCFG UTMI+ — configure the USB PHY for the correct interface mode.
Split transactions
HCSPLT setup for LS/FS devices behind HS hub — the Pi 3B keyboard connects through the LAN9514 USB hub.
W1C HCINT clear
Clear host-channel interrupt bits before/after transfers — metal-only stale-bit fix.
Data toggle
SETUP→DATA0/1→STATUS per USB spec — correct PID sequencing for control transfers.