Three sigil-kernel commits extend the HAL arch matrix from 0x548000 to 0x54D000, adding 6 seams: Apple SoC efuse/chip-ID, G3/G4/G5 CPU PVR/HID decode, Apple DART IOMMU, G5 U3/U4 DDR memory controller, Apple crypto engine (AES+TRNG), and G3/G4/G5 timebase/decrementer.
c2f5888 — SoC Efuse/Chip-ID + CPU PVR/HID
apple_chipid.sg (0x548000)
Efuse identity — chip ID, per-die ECID (unique 64-bit), board ID, production status (dev/prod), binning (active P/E/GPU core count + fused max frequency), silicon revision.
chipid_init(), chipid_read(), chipid_ecid(), chipid_board(), chipid_production(), chipid_binning() (returns active cores + fused freq), chipid_rev(), accessors. CID init=1 fuse=1 bin=1 K.ppc_cpuid.sg (0x549000)
CPU PVR decode + HID — PVR register → family (G3 750/750CX/750FX, G4 7400/7450, G5 970/970FX/970MP) + feature flags (FPU/AltiVec/64-bit), cache-line size, HID0/HID1 programming (branch prediction, data cache, nap enable).
cpuid_init(), cpuid_pvr(), cpuid_family(), cpuid_features(), cpuid_cacheline(), cpuid_hid0_set(bits), cpuid_hid1_set(bits), cpuid_nap_enable(), accessors. PID init=1 pvr=1 hid=1 K.a86856c — DART IOMMU + U3/U4 DDR Controller
apple_dart.sg (0x54A000)
DART IOMMU — per-stream (per-device) translation tables, 16KB-page IOVA map/unmap with high-water mark tracking, TLB invalidation, bypass mode for trusted devices, translation fault capture (faulting IOVA + stream ID).
dart_init(), dart_stream_attach(stream_id), dart_map(stream_id, iova, phys, pages), dart_unmap(stream_id, iova, pages), dart_tlb_invalidate(stream_id), dart_bypass(stream_id, v), dart_fault_read(), accessors. DRT init=1 map=1 flt=1 K.ppc_u3mem.sg (0x54B000)
U3/U4 DDR memory controller — 8-slot DIMM enumeration (SPD read: size/speed/rank), dual-channel 128-bit interleave + bandwidth calculation, ECC single-bit correct / multi-bit detect, scrub pass scheduling, timing configuration.
u3mem_init(), u3mem_dimm_enum(), u3mem_dimm_info(slot) (returns size/speed/rank), u3mem_interleave_bw(), u3mem_ecc_correct(addr), u3mem_ecc_detect(addr), u3mem_scrub(), accessors. U3M init=1 dimm=1 ecc=1 K.5a6c25e — Crypto Engine + Timebase/Decrementer
apple_crypto.sg (0x54C000)
Crypto engine — AES-XTS/CBC/GCM with hardware UID key (key never leaves the engine), SHA-2 hashing, TRNG entropy pulls with health-test reseed, throughput accounting (bytes encrypted/decrypted).
crypto_init(), crypto_aes_xts(key_slot, buf, len), crypto_aes_cbc(key_slot, buf, len, iv), crypto_aes_gcm(key_slot, buf, len, aad, tag), crypto_sha2(buf, len), crypto_trng_pull(buf, len), crypto_trng_reseed(), crypto_throughput(), accessors. CRY init=1 aes=1 rng=1 K.ppc_timebase.sg (0x54D000)
Time Base + Decrementer — 64-bit monotonic TB register with low→high carry-safe read, decrementer auto-reload tick interrupts, privileged TB set (boot calibration), read accounting (reads-per-second).
timebase_init(freq_hz), timebase_read() (returns 64-bit TB), timebase_read_safe() (carry-safe TBU/TBL/TBU retry), dec_set(ticks), dec_read(), dec_auto_reload(interval), timebase_set_privileged(tb64), accessors. TBR init=1 dec=1 wrap=1 K.Arch matrix now at 0x54D000.