HAL Batch 19 — AIC2/OpenPIC + TB4-Retimer/FireWire + USB-C/OHCI (sigil-kernel 4e5e85c→aed1b57)

Three sigil-kernel commits extend the HAL arch matrix from 0x526000 to 0x52B000, adding 6 seams: Apple AIC2 interrupt controller, G4/G5 OpenPIC, Apple TB4/USB4 UCM retimer, G3/G4/G5 FireWire OHCI, Apple ACM USB-C port manager, and USB OHCI root hub controller.

4e5e85c — AIC2 + OpenPIC

apple_aic.sg
0x526000

AIC2 Apple Interrupt Controller v2 — 1024-vector bitmask, IRQ fire+ack, IPI send/recv, timer IRQ, per-CPU routing

AIC2 is the second-generation Apple Interrupt Controller on M-series SoCs — it replaces the original AIC (used on A14/M1) with a larger vector space and per-CPU IRQ routing.

aic_init(cpu_count): initialises AIC2 for cpu_count CPUs; zeros the 1024-element vector enable bitmask.
aic_enable_vec(vec): enables interrupt vector vec (0–1023) in the bitmask.
aic_disable_vec(vec): disables vector vec.
aic_fire(vec): fires interrupt vector vec; increments irq_fire_count; sets the pending flag for vec.
aic_ack(vec): acknowledges (clears) the pending flag for vector vec; increments ack_count.
aic_ipi_send(src_cpu, dst_cpu): sends an IPI from src_cpu to dst_cpu; increments ipi_send_count.
aic_ipi_recv(cpu): records an IPI received on cpu; increments ipi_recv_count.
aic_timer_irq(): fires the timer interrupt; increments timer_irq_count.
aic_route_to_cpu(vec, cpu): routes vector vec to CPU cpu.
aic_vec_enabled(vec) / aic_irq_fire_count() / aic_ipi_send_count() / aic_timer_irq_count(): accessors.

AIC init=1 vec=1 ipi=1 K.

ppc_openpic.sg
0x527000

G4/G5 OpenPIC — 256-source enable+priority, IRQ fire+EOI, 8-channel IPI, timer fire, pending bitmask

OpenPIC is the interrupt controller on G4 and G5 PowerMacs — it supports up to 256 interrupt sources, each with individually programmable enable and priority, IPI via 8 dedicated channels, and per-source EOI.

openpic_init(): zeros state; initialises 256-element pending bitmask.
openpic_source_enable(src, priority): enables interrupt source src (0–255) with priority (0=lowest, 15=highest).
openpic_source_disable(src): disables source src.
openpic_fire(src): fires interrupt src; sets the corresponding bit in the pending bitmask; increments irq_fire_count.
openpic_eoi(src): End-of-Interrupt for source src — clears the pending bit; increments eoi_count.
openpic_ipi_send(channel, dest_mask): sends an IPI on channel (0–7) to CPUs in dest_mask; increments ipi_count.
openpic_timer_fire(timer): fires one of the 4 OpenPIC timers; increments timer_fire_count.
openpic_pending(src) / openpic_irq_fire_count() / openpic_eoi_count() / openpic_ipi_count(): accessors.

OPC init=1 irq=1 ipi=1 K.

76e946a — TB4/USB4 UCM retimer + G3/G4/G5 FireWire OHCI

apple_tbtret.sg
0x528000

USB-C UCM retimer — port orientation detect, USB4 Gen2/3 link training, DP alt-mode, HPD counter

The UCM (USB-C Connection Manager) retimer sits on the USB-C port, handling cable orientation detection, USB4/TB4 link training, and DisplayPort alternate-mode negotiation.

tbtret_init(): zeros state.
tbtret_connect(port, flipped): connects a cable to port; flipped=1 means CC2 is active (cable is flipped — sets orientation=FLIPPED); increments connect_count.
tbtret_disconnect(port): clears port state.
tbtret_usb4_train(port, gen): trains the USB4/TB4 link at gen (2=Gen2×2=20Gbps, 3=Gen3×2=40Gbps); sets port.link_up=1; stores gen.
tbtret_dp_altmode(port, lanes, bw_gbps): negotiates DisplayPort alt-mode — lanes (1 or 2), bw_gbps (link bandwidth).
tbtret_hpd(port): signals a Hot Plug Detect event for port; increments hpd_count.
tbtret_port_up(port) / tbtret_link_gen(port) / tbtret_connect_count() / tbtret_hpd_count(): accessors.

TRT init=1 con=1 dp=1 K.

ppc_fw_ohci.sg
0x529000

G3/G4/G5 FireWire OHCI — bus reset+generation, 63-node discovery, bus manager election, async TX/RX, isochronous channels

FireWire OHCI (IEEE 1394) is the standard FireWire controller on PowerMacs — G3 Blue & White through G5 all shipped with one or two FireWire 400/800 ports.

fw_ohci_init(): zeros state; sets bus_generation=0.
fw_ohci_bus_reset(): initiates a bus reset; increments bus_generation; resets node discovery.
fw_ohci_node_discover(node_id): discovers a FireWire node at node_id (1–63); records it in the node table; increments node_count.
fw_ohci_elect_bus_manager(): runs bus manager election; sets bus_manager_elected=1.
fw_ohci_async_tx(bytes): transmits an async packet; increments async_tx_count and async_tx_bytes.
fw_ohci_async_rx(bytes): receives an async packet; increments async_rx_count.
fw_ohci_iso_channel_open(ch): opens isochronous channel ch (0–63); sets bit ch in iso_channel_mask.
fw_ohci_iso_tx(ch, bytes): isochronous TX on channel ch; increments iso_tx_count.
fw_ohci_iso_rx(ch, bytes): isochronous RX on channel ch; increments iso_rx_count.
fw_ohci_bus_generation() / fw_ohci_node_count() / fw_ohci_async_tx_count() / fw_ohci_iso_channel_mask(): accessors.

FWC init=1 bus=1 iso=1 K.

aed1b57 — ACM USB-C port manager + USB OHCI

apple_usbc.sg
0x52A000

ACM USB-C port manager — PD3.1/EPR 140W negotiate, CC/polarity, SuperSpeed Gen2, DFP/UFP, role-swap counters

The ACM (Apple Cable Manager) USB-C port manager handles USB Power Delivery negotiation (PD3.1 with Extended Power Range up to 140W), cable orientation, USB SuperSpeed Gen2 (10Gbps) link, and DFP/UFP (Downstream/Upstream Facing Port) role negotiation.

usbc_init(): zeros all port state.
usbc_attach(port, cc_polarity): attaches a USB-C cable at port; cc_polarity (0=CC1, 1=CC2) sets the cable orientation; increments attach_count.
usbc_detach(port): clears port state.
usbc_pd_negotiate(port, voltage_mv, current_ma): negotiates a PD3.1/EPR contract — voltage_mv (up to 28000mV for 140W @ 5A); stores negotiated power; increments pd_negotiate_count.
usbc_ss_gen2_enable(port): enables SuperSpeed Gen2 (10Gbps) on port.
usbc_set_dfp(port) / usbc_set_ufp(port): set port role to DFP (host) or UFP (device).
usbc_role_swap(port): performs a PR_Swap (power role swap) or DR_Swap (data role swap); increments role_swap_count.
usbc_attached(port) / usbc_voltage_mv(port) / usbc_pd_count() / usbc_role_swap_count(): accessors.

UCM init=1 att=1 ss=1 K.

ppc_usb_ohci.sg
0x52B000

G3/G4 USB OHCI root hub — port enable/reset, device enumeration, control/bulk/interrupt transfers, IRQ accounting

USB OHCI (Open Host Controller Interface) is the USB 1.1 host controller on G3 and G4 PowerMacs — Keylargo/Pangea integrate it alongside other MAC-I/O peripherals.

ohci_init(port_count): initialises OHCI with port_count root hub ports (typically 2 or 4).
ohci_port_enable(port): enables root hub port port.
ohci_port_reset(port): resets port port; increments port_reset_count.
ohci_enumerate(port): enumerates a USB device on port; increments device_count.
ohci_control_transfer(bytes): performs a USB control transfer; increments ctrl_count.
ohci_bulk_transfer(bytes): USB bulk transfer; increments bulk_count; adds bytes to bulk_bytes.
ohci_interrupt_transfer(bytes): USB interrupt transfer; increments intr_count.
ohci_irq(): records a USB host controller interrupt; increments irq_count.
ohci_device_count() / ohci_bulk_bytes() / ohci_ctrl_count() / ohci_irq_count(): accessors.

OHC init=1 enm=1 xfr=1 K.

Arch matrix summary

Address	Surface	Commit	Platform
`0x526000`	apple_aic.sg — AIC2 Apple Interrupt Controller v2	`4e5e85c`	Apple Silicon (M-series)
`0x527000`	ppc_openpic.sg — G4/G5 OpenPIC	`4e5e85c`	PowerPC G4/G5
`0x528000`	apple_tbtret.sg — TB4/USB4 UCM retimer	`76e946a`	Apple Silicon
`0x529000`	ppc_fw_ohci.sg — G3/G4/G5 FireWire OHCI	`76e946a`	PowerPC G3/G4/G5
`0x52A000`	apple_usbc.sg — ACM USB-C port manager	`aed1b57`	Apple Silicon
`0x52B000`	ppc_usb_ohci.sg — G3/G4 USB OHCI root hub	`aed1b57`	PowerPC G3/G4

The HAL arch matrix now extends to 0x52B000. Batch 19 completes the interrupt-controller pair (AIC2 for Apple Silicon, OpenPIC for G4/G5), the Thunderbolt/FireWire connectivity layer, and the USB-C/USB-1.1 port management tier — covering the full connectivity stack from power negotiation through isochronous data on both the Apple Silicon and PowerPC sides of the matrix.