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HAL Batch 15 — AWDL/VMX + AMC/SMU + TB4/K2-Bridge

June 23, 2026 · sigil-kernel 473c855 + bb757da + d34c8ba · Sigil-Docs
kernel hal apple-silicon powerpc hardware 0.7.0

Three sigil-kernel commits extend the HAL arch matrix from 0x50A000 to 0x50F000, adding 6 seams: Apple AWDL peer-to-peer Wi-Fi, G4/G5 AltiVec/VMX context, Apple LPDDR5 AMC memory controller, G5 PowerMac SMU, Apple Thunderbolt 4/USB4 port manager, and G5 K2/Shasta south bridge.


473c855 — AWDL + G4/G5 AltiVec/VMX

apple_awdl.sg
0x50A000
AWDL peer-to-peer Wi-Fi (AirDrop/AirPlay transport)
AWDL (Apple Wireless Direct Link) is the Wi-Fi-based peer-to-peer protocol underlying AirDrop, AirPlay, and Handoff. It operates over a 3-channel hop sequence that periodically switches frequencies to coexist with regular Wi-Fi. awdl_init(): zeros state; initialises the 8-slot peer table. awdl_peer_join(mac): adds a peer (by MAC address) to the peer table; increments join_count. awdl_peer_leave(mac): removes a peer; increments leave_count. awdl_hop_channel(): advances the channel hop sequencer — cycles through the 3-channel AWDL sequence (channels 6, 44, 149 in rotation); returns the new channel. awdl_tx_frame(bytes) / awdl_rx_frame(bytes): increment TX/RX frame counters and tx_bytes/rx_bytes. awdl_peer_count() / awdl_current_channel() / awdl_tx_frames() / awdl_rx_frames(): accessors. AWD init=1 per=1 hop=1 K.
ppc_vmx.sg
0x50B000
G4/G5 AltiVec/VMX — enable gate, context save/restore, VSCR saturation
G4/G5 AltiVec (called VMX on G5 following POWER4 naming) provides 128-bit SIMD. vmx_init(): zeros state; clears vmx_enabled. vmx_enable(): sets vmx_enabled=1 (enables AltiVec/VMX for the current task, analogous to setting MSR[VEC]). vmx_disable(): clears vmx_enabled. vmx_ctx_save(ctx): saves the VMX context — captures 33 VR words (32 VRs × 4 bytes proxy + VSCR) into ctx; clears vmx_enabled. vmx_ctx_restore(ctx): restores the 33 VR words from ctx; sets vmx_enabled=1. vmx_op(): performs a VMX operation (proxy); increments ops_count; updates vscr_sat (saturation bit — set if any saturating operation would overflow). vmx_vscr_sat() / vmx_ops(): telemetry. VMX init=1 ctx=1 sat=1 K.

bb757da — LPDDR5 AMC + G5 SMU

apple_amc.sg
0x50C000
LPDDR5 AMC (Apple Memory Controller), 4-channel with BW split
The Apple Memory Controller (AMC) manages LPDDR5 DRAM across 4 channels, with bandwidth partitioned between CPU, GPU, and ANE. amc_init(ch0_bw, ch1_bw, ch2_bw, ch3_bw): initialises 4 channels with per-channel bandwidth splits (GB/s allocation); each channel's bandwidth is divided between CPU, GPU, and ANE agents. amc_access(agent, bytes): records a memory access by agent (CPU=0, GPU=1, ANE=2); increments agent_mb[agent] (in MB). amc_refresh(): performs a DRAM refresh cycle; increments refresh_count. amc_ecc_correct(): records a correctable ECC error; increments ecc_corr. amc_ecc_fatal(): records an uncorrectable ECC error; increments ecc_fatal. amc_throttle(enable): sets/clears the bandwidth throttle gate (when set, all accesses are blocked). amc_agent_mb(agent) / amc_total_refresh() / amc_ecc_corr() / amc_ecc_fatal() / amc_throttled(): accessors. AMC init=1 acc=1 ecc=1 K.
ppc_smu.sg
0x50D000
G5 PowerMac SMU (VID/voltage, 9-zone fan PWM, overtemp/shutdown)
The G5 PowerMac's SMU (System Management Unit) handles CPU voltage ID (VID) control, 9-zone variable-speed fan management, overtemperature protection, and orderly shutdown. smu_init(): zeros all state. smu_set_vid(vid): sets the CPU voltage ID (vid selects a voltage step from the VID table); stores voltage_mv. smu_fan_set_pwm(zone, pwm_pct): sets the PWM duty cycle (0–100%) for fan zone zone (0–8). smu_fan_set_rpm(zone, rpm): records the actual RPM reading for zone. smu_fan_ramp(zone, temp_c): ramps fan zone based on temperature — at 70°C and above, increases PWM by 10% per degree above threshold (capped at 100%). smu_overtemp(zone): records an overtemperature event for zone; increments overtemp_count. smu_shutdown(reason): initiates orderly shutdown with LED sequencing — sets shutdown_pending=1, stores shutdown_reason (reason: 0=user, 1=overtemp at 95°C, 2=SMC command). smu_shutdown_pending() / smu_voltage_mv() / smu_fan_pwm(zone) / smu_overtemp_count(): accessors. SMU init=1 fan=1 sdn=1 K.

d34c8ba — TB4/USB4 port manager + G5 K2/Shasta south bridge

apple_tb4.sg
0x50E000
Thunderbolt 4/USB4 4-port manager (DP/PCIe/USB tunnels, BW accounting, device auth)
Thunderbolt 4 (which is a superset of USB4 Gen 3×2) manages 4 ports, each capable of simultaneously tunneling DisplayPort, PCIe, and USB 3.x traffic. tb4_init(): zeros all port state. tb4_connect(port, speed_gbps, dp_lanes, pcie_lanes, usb_speed_gbps): connects a device to port (0–3) — speed_gbps is the TB4/USB4 link speed (10/20/40); dp_lanes (0–4) requests DisplayPort lanes; pcie_lanes (0–4) requests PCIe lanes; usb_speed_gbps sets USB protocol speed. Sets P*_ONLINE=1. tb4_open_tunnel(port, type): opens a tunnel — type: DP=0, PCIe=1, USB=2. Increments the appropriate tunnel counter. Accounts for the bandwidth consumed. tb4_disconnect(port): clears port state and all tunnel counters for port. tb4_auth_device(port, ok): records device authentication result — if ok=0 increments auth_fail_count; if ok=1 increments auth_ok_count. tb4_port_online(port) / tb4_tunnel_count(port, type) / tb4_auth_ok() / tb4_auth_fail(): accessors. TB4 init=1 con=1 tun=1 K.
ppc_k2_bridge.sg
0x50F000
G5 K2/Shasta south bridge (ATA/USB/FireWire/DMA/IRQ/PCI-X)
The K2 (UniNorth 2 "Shasta") is the south bridge on G5 PowerMacs — integrating 2 ATA channels, 6 USB 2.0 ports, 2 FireWire ports (400 + 800), a PCI-X bus, DMA engine, and the K2-PIC interrupt controller. k2_init(): zeros all state. k2_ata_attach(channel): attaches an ATA drive to channel 0 or 1; sets ata_ch*_online=1. k2_usb_port_attach(port): attaches a USB device to port (0–5); sets bit port in usb_bitmask. k2_fw_attach(port): attaches a FireWire device (port 0=FW400, port 1=FW800). k2_dma_transfer(bytes): models a DMA transfer; increments dma_count. k2_irq_dispatch(vec): dispatches an IRQ through the K2-PIC; increments irq_count. k2_set_pcix_latency(timer): sets the PCI-X latency timer value. k2_usb_bitmask() / k2_ata_online(ch) / k2_dma_count() / k2_irq_count(): accessors. K2B init=1 att=1 irq=1 K.

Arch matrix now at 0x50F000.