HAL Batch 14 — ANE IPC/HT-UMA + SEP IPC/PMU-HDEP (sigil-kernel 8bd281d+3f06418)

Apple Neural Engine IPC (inference queue + thermal throttle)
apple_ane_link.sg is the IPC layer above the ANE hardware — coordinating inference requests between the kernel and the ANE coprocessor, with thermal throttle awareness. ane_link_init(): zeros state. ane_link_submit(model_id, input_buf, output_buf): submits an inference job to the 8-slot queue — model_id identifies the CoreML model; sets busy=1. If thermal throttle is active (throttled=1), the submission is rejected (returns 0). Increments submit_count and ops_count (a proxy for total operations). ane_link_complete(): signals completion — advances done_count, clears busy. ane_link_set_throttle(v): sets/clears the thermal throttle gate (1=throttled). ane_link_busy() / ane_link_done() / ane_link_ops(): status accessors. ANE init=1 sub=1 cpl=1 K.

G5 HyperTransport + U3 UMA coherence controller
The U3 "Kodiak" northbridge on G5 Macs combines the HyperTransport link to the processor with a UMA (Unified Memory Architecture) coherence controller. ht_uma_init(width, freq_mhz, bw_gbps): initialises the HT link and coherence controller — width (8 or 16 bits), freq_mhz (800 for G5), bw_gbps (bandwidth in GB/s). ht_uma_tx_packet(data) / ht_uma_rx_packet(): transmit/receive an HT packet; increment tx_count/rx_count. ht_uma_dma_transfer(len): models a DMA transfer of len bytes; increments dma_count. ht_uma_irq_dispatch(vec): dispatches an interrupt vector via the HT IRQ path; increments irq_count. ht_uma_probe_hit(): records a cache coherence probe hit (another processor snooping a cache line); increments probe_hits. ht_uma_crc_error(): sets crc_error=1 (link CRC error). ht_uma_link_ok(): returns 1 if crc_error=0. HTP init=1 pkt=1 uma=1 K.

Secure Enclave Processor IPC (updated seam — session lifecycle, Touch/Face ID, key-ops)
This commit updates apple_sep.sg to the full IPC model. sep_init(): zeros state; initialises session table. sep_session_open(): opens a SEP session; increments session_count. sep_session_close(): closes the current session. sep_auth_request(type): submits an authentication request — type selects TOUCH_ID=0 or FACE_ID=1; increments auth_request_count. sep_auth_result(success): records the authentication result; if success=1 increments auth_success_count. sep_key_lock() / sep_key_unlock(): locks/unlocks the key-op gate (key_locked=1/0). sep_key_op(op): performs a key operation (op: 0=encrypt, 1=decrypt, 2=sign, 3=verify) — fails (returns 0) if key_locked=1; otherwise increments key_op_count. sep_key_op_count() / sep_auth_success_count(): telemetry. SEP init=1 aut=1 key=1 K.

G4/G5 PMU + HDEP (DVFS, sleep/wake, battery, thermal emergency)
The G4/G5 PMU includes HDEP (Hardware-Driven Efficiency Policy) — a power management subsystem that handles CPU frequency/voltage scaling (DVFS), sleep/wake cycles, battery monitoring, and thermal emergency shutdown. pmu_hdep_init(): zeros all state; sets on_battery=0, battery_pct=100. pmu_hdep_dvfs_step(freq_mhz, voltage_mv): performs a DVFS step — records the new freq_mhz and voltage_mv; increments dvfs_count. pmu_hdep_sleep() / pmu_hdep_wake(): sleep/wake cycle — increment sleep_count/wake_count. pmu_hdep_set_battery(pct, voltage_mv, charging): updates battery state; sets on_battery if charging=0. pmu_hdep_thermal_emergency(zone): records a thermal emergency for zone; increments thermal_emergency_count. pmu_hdep_on_battery() / pmu_hdep_freq_mhz() / pmu_hdep_dvfs_count() / pmu_hdep_thermal_emergencies(): accessors. PMU init=1 dvf=1 slp=1 K.