Three sigil-kernel commits extend the HAL arch matrix from 0x4FA000 to 0x4FF000, completing the 0x4E0000→0x4FF000 arch-matrix range — 35 Apple+PowerPC paired seams, 70 seams total across this block. The six new seams: Apple AGX GPU command ring, G3/G4/G5 PPC Decrementer + timebase, Apple PCIe root complex (updated to 4-port), G3/G4/G5 SPI+I2C dual bus, Apple DCP image scaler, and G3/G4/G5 RTC + 128B PRAM. Next pass opens 0x500000+.
Section 1: 5c8e391 — AGX GPU command ring + PPC Decrementer
apple_gpu_cmd.sg (0x4FA000) — AGX GPU front-end submit ring (RENDER/COMPUTE/BLIT/PRESENT)
gpu_cmd_init()
Initialises the 16-slot ring at
head=tail=0. The AGX GPU (used in M1/M2/M3/M4) processes command buffers through a front-end ring; this seam models that submit path.gpu_cmd_submit(type)
Submits a command buffer of the given type — RENDER=0, COMPUTE=1, BLIT=2, PRESENT=3. Increments the per-type counter (
render_count/compute_count/blit_count/present_count). Increments submit_count and monotonic fence_id. Sets busy=1. BUSY guard prevents double-submit before completion. Advances tail mod 16.gpu_cmd_complete()
Simulates HW completion — advances
ring_head, increments done_count, clears busy when done_count == submit_count.gpu_cmd_busy() / gpu_cmd_fence() / gpu_cmd_done()
Status helpers. GPU init=1 sub=1 cmp=1 K.
ppc_decrementer.sg (0x4FB000) — PPC decrementer + timebase model
dec_init(tb_freq, kern_hz)
Initialises the decrementer; computes
reload = tb_freq / kern_hz (the number of timebase ticks per kernel timer period — e.g. at 33MHz timebase and 100Hz kern, reload = 330000). The PPC Decrementer is a countdown register (SPR 22) that fires a Decrementer Interrupt (vector 0x900) when it reaches zero, driving the kernel timer tick. The Timebase (TBL/TBU, SPRs 268/269) is a monotonically increasing 64-bit counter.dec_tick(n)
Advances the timebase by
n ticks (accumulates tb_lower); if the accumulated ticks ≥ dv (the current decrementer value), fires a DEC interrupt (increments jiffies), reloads dv = reload.dec_jiffies() / dec_tb_lower() / dec_reload()
Accessors. DEC init=1 tck=1 tb=1 K.
Section 2: 1b4ec0e — PCIe root complex + SPI/I2C bus
apple_pcie.sg (0x4FC000) — 4-port PCIe root complex (updated seam, Gen1–4, BAR enumeration)
pcie_init()
Zeros all port state. Apple Silicon's PCIe root complex connects NVMe SSD, Ethernet, Thunderbolt/USB4, and Wi-Fi/BT. This commit updates
apple_pcie.sg to 4 ports.pcie_train_link(port, gen, width)
Trains the PCIe link on
port (0–3) to the given gen (1–4 = Gen1–Gen4) and width (1/2/4 = x1/x2/x4 lanes). Sets P*_LINK=1 in the port's CTRL register. Tests exercised: port 0 = NVMe Gen4×4, port 1 = Ethernet Gen3×1, port 2 = Thunderbolt Gen4×4.pcie_enum_bar(port, bar_idx, size)
Enumerates a BAR (Base Address Register) for the device on
port — records bar_size and bar_addr (assigned as 0x80000000 + port×0x10000000 + bar_idx×size).pcie_link_up(port) / pcie_bar_addr(port, bar_idx)
Accessors. PCI init=1 trn=1 enm=1 K.
ppc_spi_i2c.sg (0x4FD000) — G3/G4/G5 dual SPI+I2C bus controller
spi_i2c_init()
Zeros all counters. On G3/G4/G5 Macs, SPI and I2C share a combined bus controller seam handling both protocols.
spi_xfer(data)
SPI full-duplex transfer — sends
data, returns (data + 1) % 256 as the synthetic received byte (echo+1 model, byte-wrap at 255). Increments spi_tx_count and spi_rx_count.i2c_write(addr, reg, data)
I2C write transaction — logs
last_i2c_addr, last_i2c_reg, last_i2c_data; increments i2c_tx_count.i2c_read(addr, reg)
I2C read transaction — returns
(addr + reg) % 256 as synthetic data; increments i2c_rx_count. Note: no hex literals (cc0 parse constraint) and no parenthesised initialiser expressions. SII init=1 spi=1 i2c=1 K.Section 3: 93e702f — DCP image scaler + RTC/PRAM
apple_dcp_scaler.sg (0x4FE000) — DCP image scaler (nearest/bilinear/Lanczos)
dcp_scaler_init()
Zeros all state. The DCP (Display Coprocessor) on Apple Silicon includes a hardware image scaler used for display scaling, screen recording, and video compositing.
dcp_scaler_config(src_w, src_h, dst_w, dst_h, algo)
Configures a scale operation —
algo selects NEAREST=0, BILINEAR=1, LANCZOS=2. Validates resolution: if src_w == 0 or src_h == 0, increments err_count and returns -1. Computes scale_x_100 = (dst_w × 100) / src_w and scale_y_100 = (dst_h × 100) / src_h (×100 fixed-point ratio).dcp_scaler_run()
Executes the scale pass; increments
frame_count.dcp_scaler_scale_x() / dcp_scaler_scale_y() / dcp_scaler_frames() / dcp_scaler_errors()
Accessors. DSC init=1 cfg=1 scl=1 K.
ppc_rtc.sg (0x4FF000) — G3/G4/G5 RTC + 128B PRAM proxy
rtc_init()
Zeros all state; sets
unix_time=0, sub_ticks=0. The G3/G4/G5 RTC keeps wall-clock time, and PRAM (Parameter RAM — 128 bytes on these Macs) stores firmware settings: boot device, display mode, AppleTalk zone, and custom parameters.rtc_set_time(t) / rtc_tick() / rtc_get_time()
rtc_set_time(t): sets the Unix timestamp. rtc_tick(): advances sub-second counter; when sub_ticks reaches 100 (100 ticks per second model), wraps to 0 and increments unix_time. rtc_get_time(): returns current unix_time.rtc_set_alarm(t) / rtc_alarm_fired()
rtc_set_alarm(t): sets an alarm Unix timestamp. rtc_alarm_fired(): returns 1 if unix_time >= alarm_time (and alarm_time > 0).pram_write(offset, val) / pram_read(offset) / pram_write_protect(enable)
pram_write(offset, val): writes 1 byte to PRAM at offset (0–127); sets pram_dirty=1. pram_read(offset): reads 1 byte. pram_write_protect(enable): sets pram_wp (write-protect gate — when set, pram_write is a no-op). RTC init=1 prm=1 alm=1 K.Milestone summary: 0x4E0000→0x4FF000 complete
The 0x4E0000→0x4FF000 arch-matrix range is complete: 35 Apple+PowerPC paired seams, 70 seams total. Combined with earlier batches (0x4BA000→0x4DF000), the HAL now spans from 0x4BA000 to 0x4FF000. Next pass opens 0x500000+.
| Address | Seam | Arch | Commit |
|---|---|---|---|
0x4FA000 | apple_gpu_cmd.sg — AGX GPU front-end submit ring | Apple Silicon | 5c8e391 |
0x4FB000 | ppc_decrementer.sg — PPC Decrementer + timebase | G3/G4/G5 | 5c8e391 |
0x4FC000 | apple_pcie.sg — 4-port PCIe root complex | Apple Silicon | 1b4ec0e |
0x4FD000 | ppc_spi_i2c.sg — dual SPI+I2C bus controller | G3/G4/G5 | 1b4ec0e |
0x4FE000 | apple_dcp_scaler.sg — DCP image scaler | Apple Silicon | 93e702f |
0x4FF000 | ppc_rtc.sg — RTC + 128B PRAM proxy | G3/G4/G5 | 93e702f |