Three sigil-kernel commits push the HAL arch matrix from 0x4F4000 to 0x4F9000, adding 6 seams: Apple audio/CLPD routing controller, G5 U3H/U4 ECC memory controller, Apple M1 AMX matrix tile coprocessor, G4 Velocity Engine DSP queue, Apple T2 security chip bridge, and G3/G4 cache topology probe.
edd5146 — Audio/CLPD controller + G5 ECC
apple_audio_ctrl.sg
0x4F4000
CLPD audio routing fabric (5 endpoints, 4 sample rates). The Apple CLPD (Core Low-Power DSP) routing fabric connects audio streams to output endpoints.
audio_ctrl_init(): zeros all state. audio_ctrl_set_route(endpoint): selects the active output endpoint — 0=speaker, 1=headphone, 2=HDMI, 3=AirPlay, 4=USB audio; rejects values outside 0–4. audio_ctrl_set_rate(rate_hz): configures the sample rate — accepts 44100, 48000, 96000, or 192000 Hz only; rejects any other value. audio_ctrl_set_volume(vol): sets volume 0–100. audio_ctrl_mute() / audio_ctrl_unmute(): sets muted=1 / muted=0. audio_ctrl_tick(): advances frames_out counter (frames processed). audio_ctrl_route() / audio_ctrl_rate() / audio_ctrl_volume() / audio_ctrl_muted() / audio_ctrl_frames_out(): accessors. AC init=1 rte=1 vol=1 K.
ppc_ecc.sg
0x4F5000
G5 U3H/U4 2-channel ECC controller (SEC/DED). The G5's memory controller (U3H "Kodiak" or U4) implements ECC (Error-Correcting Code) over two DDR channels. SEC = Single Error Correct; DED = Double Error Detect.
ecc_init(): zeros all state; sets ch0_ok=1, ch1_ok=1 (both channels healthy). ecc_sbe(channel, addr, syndrome): handles a Single-Bit Error (correctable) — logs the addr and syndrome (the ECC check bits that identified the error) for channel channel (0 or 1), increments total_corr (total corrected errors); the SBE is corrected in hardware and the system continues. ecc_mbe(channel): handles a Multi-Bit Error (fatal, uncorrectable) — clears ch*_ok for the failing channel (marking it unhealthy), increments total_fatal; an MBE would trigger a machine check in real hardware. ecc_scrub(): background memory scrub pass — increments scrub_count. ecc_ch0_ok() / ecc_ch1_ok() / ecc_total_corr() / ecc_total_fatal(): status accessors. ECC init=1 sbe=1 mbe=1 K.
1cada75 — AMX matrix coprocessor + G4 VE DSP
apple_amx.sg
0x4F6000
M1 AMX tile registers (lazy enable, MAC, context save/restore). The AMX (Apple Matrix eXtensions) is a matrix coprocessor built into M1 — accelerating BLAS-level matrix operations (multiply-accumulate over 32×16-byte tiles X, Y, Z). Like AltiVec and FPU, it uses lazy enable via a trap.
amx_trap_enable(task): called on AMX-unavailable trap — grants AMX to task; sets amx_enabled=1. amx_load_x(task, val): loads a value into X0 tile (proxy for the full tile load). amx_load_y(task, val): loads a value into Y0 tile. amx_mac(task): matrix multiply-accumulate — Z0 = X0 + Y0 (proxy sum representing the MAC result in the Z tile). amx_save(task): saves AMX context (X0, Y0, Z0) into task; marks ctx_dirty=0; clears amx_enabled=0 (lazy release — the context is saved, AMX is logically disabled for this task until it traps again). amx_restore(task): restores X0, Y0, Z0 from task; sets amx_enabled=1. amx_in_use(): returns amx_enabled. AMX init=1 mac=1 sav=1 K.
ppc_ve_dsp.sg
0x4F7000
G4 Velocity Engine DSP queue (FIR/IIR/FFT/VSUM). The G4's Velocity Engine (AltiVec VMX) is also used as a DSP for signal processing operations. This seam models a dedicated DSP submit ring for structured DSP jobs.
ve_dsp_init(): initialises the 8-slot submit ring. ve_dsp_submit(op, n_samples, src_buf, dst_buf): submits a DSP job — op selects FIR=0, IIR=1, FFT=2, VSUM=3; n_samples is the number of input samples; src_buf/dst_buf are I/O buffers; the job is appended to ring[tail] with a cycle estimate (FIR: n×4, IIR: n×6, FFT: n×12, VSUM: n×2); advances tail mod 8, sets busy=1; the BUSY gate prevents double-add/underflow if ve_dsp_complete() hasn't been called between submits. ve_dsp_complete(): simulates completion — advances ring_head, increments done_count, clears busy when ring is empty. ve_dsp_busy() / ve_dsp_done_count(): helpers. VED init=1 sub=1 cmp=1 K.
5563ec5 — T2 security bridge + G3/G4 cache probe
apple_t2.sg
0x4F8000
T2 security chip bridge (secure boot + SSD AES + Touch ID + HMAC verify). The T2 is Apple's dedicated security chip in Intel-era Macs (2018–2021), handling secure boot, encrypted SSD (always-on AES), Touch ID, and boot artifact integrity.
t2_init(): sets boot_policy=FULL_SECURITY (the strictest policy — only Apple-signed OS). t2_set_boot_policy(policy): sets boot policy — FULL_SECURITY=0, MEDIUM_SECURITY=1, NO_SECURITY=2. t2_ssd_load_key(key_material): loads the AES-256 key into the SSD encryption engine; stores a hash of the key material, sets ssd_key_loaded=1. t2_ssd_unlock(): unlocks the SSD (decryption enabled); returns 1 only if ssd_key_loaded=1, else fails. t2_touchid_enroll(template): enrolls a Touch ID fingerprint template; sets biom_enrolled=1. t2_verify_artifact(artifact_id, hmac): verifies a boot artifact's HMAC — simulates policy check: if artifact_id % 3 == 0 the HMAC is valid (ALLOWED); otherwise the check fails (DENIED), increments revoke_cnt. T2 init=1 ssd=1 bid=1 K.
ppc_cache_probe.sg
0x4F9000
G3/G4 cache topology probe (PVR-driven). On PowerPC, the PVR (Processor Version Register — SPR 287) identifies the exact CPU version and stepping, which determines cache topology since G3 and G4 variants have different cache configurations.
cache_probe_init(pvr): initialises the probe; stores pvr. cache_probe_run(pvr): executes cache topology detection based on pvr. For G3 (PVR 0x0008xxxx): L1 is 32KB I + 32KB D; L2 is 256KB–1MB (configurable), with optional parity. For G4 (PVR 0x000Cxxxx or 0x800Cxxxx): L1 is 32KB I + 32KB D; L2 is 256KB–1MB with parity; L3 is 2MB–4MB DDR-SRAM, present only if L3_PRESENT=1 (some G4 configurations have no L3). cache_probe_l1_i() / cache_probe_l1_d() / cache_probe_l2_kb() / cache_probe_l2_parity() / cache_probe_l3_kb() / cache_probe_l3_present(): topology accessors. cache_probe_count(): returns number of probe passes (for multi-pass boot). CPR init=1 g3=1 g4=1 K.
Arch matrix: 0x4F4000 → 0x4F9000
HAL batch 11 covers the multimedia processing, memory reliability, compute acceleration, and security/topology tier. The six new seams land across three commits:
| Seam | Address | Commit | Domain |
|---|---|---|---|
apple_audio_ctrl.sg | 0x4F4000 | edd5146 | Audio routing fabric — CLPD, 5 endpoints, 4 rates |
ppc_ecc.sg | 0x4F5000 | edd5146 | G5 U3H/U4 ECC — SEC/DED, 2-channel, scrub |
apple_amx.sg | 0x4F6000 | 1cada75 | M1 AMX — lazy enable, MAC, ctx save/restore |
ppc_ve_dsp.sg | 0x4F7000 | 1cada75 | G4 Velocity Engine DSP — FIR/IIR/FFT/VSUM ring |
apple_t2.sg | 0x4F8000 | 5563ec5 | T2 bridge — secure boot, SSD AES, Touch ID, HMAC |
ppc_cache_probe.sg | 0x4F9000 | 5563ec5 | G3/G4 cache probe — PVR-driven topology detection |
Audio routing fabric, ECC memory protection, AMX matrix tiles, VE DSP queue, T2 secure enclave bridge, and cache topology detection: the HAL matrix now spans a complete tier of multimedia, reliability, acceleration, and security hardware.