Nintendo Switch (#66, 2017) joins the fleet — NVIDIA Tegra X1 (ARM Cortex-A57 quad-core + Maxwell GPU, 1280×720). sigil-drivers adds IDE/ATA PIIX3 (soft-reset, DRIVE_HEAD select, ata_identify 16-bit data port, CLS_STORAGE) and VGA Sequencer + Graphics Controller (MAP_MASK/BIT_MASK r/w, GFX_MISC text-range, READ_MAP plane select, CLS_DISPLAY). The x86 display driver stack is now complete: DAC palette + CRTC timing + Sequencer/GC plane control + BGA mode-set. (sigil-retropie 6d33014; sigil-drivers 4b494d0, 8e33177)
Nintendo Switch — system #66
Commit 6d33014 — cores/switch.sg.
switch_render outputs to the 720p framebuffer./roms/game.nsp via the cap-gated ROM path.The Switch spans 40 years of the fleet's timeline. At one end: the Atari 2600 (1977), MOS 6507, 160×192, 1.19MHz. At the other: the Switch (2017), ARMv8, 1280×720, 1.02GHz, Maxwell shaders. System #66 is also the most architecturally modern GPU modeled — Vulkan-capable, tile-based, 256 CUDA cores — and the first time a 64-bit ARM core appears in a fleet ROM core.
IDE/ATA PIIX3 driver
Commit 4b494d0 — drivers/storage/ide-ata.
The Intel PIIX3 (82371SB) is the PCI IDE controller found in virtually every PC from the mid-1990s through the early 2000s, providing ATA-33 DMA to hard disks and CD-ROMs. Modeling it is required for x86 disk I/O on systems that predate AHCI — including the target machines for sigil-os#18 bare-metal x86 boot.
0x1F0 (16-bit inw/outw), error 0x1F1, sector count 0x1F2, LBA low/mid/high 0x1F3–0x1F5, DRIVE_HEAD 0x1F6, command/status 0x1F7. Alt-status 0x3F6 (no-IRQ status read).0x3F6 = 0x04 (SRST assert) → 0x02 (SRST deassert). ata_wait_not_busy() polls status BSY bit → 0. Standard ATA software reset per ATA-2 spec.0xE0 (master, LBA mode). 0xF0 for slave. Both master and slave addressable on the primary channel.0xEC (ATA IDENTIFY) → poll BSY=0 + DRQ=1 → read 256×16-bit words from 0x1F0. Returns drive model string, sector count, and capability flags.ata_probe: STATUS ≠ 0xFF (floating bus guard). Live QEMU: STATUS=0x00 after reset (no disk, controller present). No drive detected (dp=0) is valid — controller probed, no media. CLS_STORAGE dispatcher. State at 0x910000.VGA Sequencer + Graphics Controller
Commit 8e33177 — drivers/display/vga-seq.
The VGA Sequencer and Graphics Controller are two of the five functional units inside the VGA chip (alongside the CRTC, DAC, and Attribute Controller). They control how pixel data is read from and written to VGA video memory — which bitplanes are active, how bytes map to pixels, and how the text-mode address window is configured. Without modeling them, the kernel cannot correctly initialize VGA text mode 3 or any planar graphics mode from first principles.
Sequencer — I/O 0x3C4 (index) / 0x3C5 (data)
0x03 (planes 0+1 — character codes and attributes). Planar graphics: 0x0F (all four planes).0x03 (both reset bits set = running). Writing 0x01 holds the sequencer in reset — used during mode switches.Graphics Controller — I/O 0x3CE (index) / 0x3CF (data)
0xFF = all 8 pixels in the byte are affected. 0x80 = only the leftmost pixel. Used for sub-byte pixel blitting in planar modes.0x0E = 0xB800 text range, 32KB window (standard CGA/text mode). 0x05 = 0xA000, 64KB (EGA/VGA graphics). Controls which physical address range the VGA window appears at.Live QEMU text mode 3 verification: MAP_MASK=0x03, BIT_MASK=0xFF, GFX_MISC=0x0E, SEQ_RESET=0x03, SEQ_MEM_MODE=0x02. MAP_MASK r/w (0x0A/0x05) + BIT_MASK r/w (0xAA/0x55) + READ_MAP r/w (plane 0–3) all verified against live QEMU register state. CLS_DISPLAY dispatcher: CTL_SEQ_READ/WRITE, CTL_GFX_READ/WRITE, CTL_PLANE_SET/ALL. State at 0x920000.
Complete VGA display driver stack — 5 layers
With the Sequencer + Graphics Controller landed, the x86 display stack is complete. The kernel can configure any VGA output mode — from legacy text mode 3 to planar EGA/VGA graphics to the linear BGA framebuffer — entirely through Sigil-level port I/O, without any BIOS calls.
| Layer | Driver | I/O Address | Controls |
|---|---|---|---|
| Mode-set | bga (0x890000) |
0x1CE / 0x1CF | Resolution + BPP (post-BIOS linear framebuffer) |
| Sequencer | vga-seq (0x920000) |
0x3C4 / 0x3C5 | Plane write mask, memory mode, sequencer reset |
| GFX Ctrl | vga-seq (0x920000) |
0x3CE / 0x3CF | Bit mask, read map plane select, memory map window |
| CRTC | vga-crtc (0x8F0000) |
0x3D4 / 0x3D5 | Raster timing, cursor position, scroll offset |
| DAC | vga-dac (0x900000) |
0x3C7 – 0x3C9 | 256-entry 6-bit RGB palette |
The full mode matrix now reachable under kernel control:
- Text mode 3: SEQ_RESET=0x03, MAP_MASK=0x03, GFX_MISC=0x0E, CRTC timing = 80×25 chars. No BIOS required.
- Planar mode 12h (640×480 4bpp): MAP_MASK=0x0F, BIT_MASK per pixel, READ_MAP per plane.
- Mode 13h (320×200 256-color): CHAIN4=1, single-plane linear byte addressing.
- BGA linear framebuffer: BGA index 0x01 width, 0x02 height, 0x03 BPP — full-color post-BIOS mode.
The driver stack is the foundation for the x86 real-silicon boot work in sigil-os#18 — every display output path, from BIOS-emulation VGA through modern linear framebuffer, is now modeled and QEMU-verified in Sigil before it runs on bare metal.