RetroPie Fleet Batch: Atari 8-bit, MSX Turbo-R, Sega Saturn, Sega 32X — Systems #41–44

sigilOS RetroPie ships 4 new LAUNCHABLE systems in a single batch: Atari 800 (#41), MSX Turbo-R (#42), Sega Saturn (#43), and Sega 32X (#44). Together with WonderSwan (#45, already landed), the fleet is now at 45 LAUNCHABLE systems. All run as EL0 apps — cap-scoped ROM access, no ambient filesystem. (sigil-retropie 2bc19e0, 521c058, 31fc8c9, 8400f43)

sigilOS RetroPie launcher showing WonderSwan as system #45 — sigilOS RetroPie launcher — WonderSwan (system #45) in the 45-system fleet

Fleet count: 45 LAUNCHABLE

The RetroPie fleet now covers 45 systems (#1–#45). Every system in the fleet runs as an EL0 app under the capability security model: ROM access is cap-scoped per-slot, the app cannot walk the filesystem, and there is no ambient read path. The launcher itself is a Lumen WM surface — not a shell script, not a subprocess menu.

Atari 800 — system #41

Commit 2bc19e0. cores/at8.sg uses first-def-wins layering over m6502.sg to override m6_read / m6_write with the Atari 800 memory map:

$0000–$BFFF — 48 KB RAM
$D000–$D01F — GTIA registers (COLPF0–3, COLPM0–3, COLBK)
$E000–$FFFF — 8 KB OS ROM

at8_color() performs NTSC YIQ color decode from the GTIA color register. GR.0 text render: 40×24 character grid, screen RAM at $9C40, character ROM at $E800. at8_bit() extracts glyph bits MSB-first. core_load reads the 6502 reset vector from $FFFC–$FFFD.

uart=48 PASS. apps/atari800 (38,560 B, arm-el0), loads /roms/game.rom (8 KB cap).

MSX Turbo-R — system #42

Commit 521c058. cores/msx_turbo.sg uses first-def-wins layering over msx2.sg with core_id=1991. The R800 CPU is Z80-compatible; the shared z80.sg core is reused without modification.

Hardware: V9938 graphics, AY PSG, slot layout unchanged from MSX2. The Turbo-R variant is a clean delta on top of the MSX2 foundation — msx2_app.sg entry point is reused.

uart=49 PASS. apps/msx_turbo (52,944 B, arm-el0), loads /roms/game.rom.

Sega Saturn — system #43

Commit 31fc8c9. The Saturn introduces the Hitachi SH-2 CPU to the fleet via cores/sh2.sg.

SH-2 CPU (`cores/sh2.sg`)

16-bit fixed-width big-endian ISA. 16 general-purpose registers + PC/SR/PR/GBR + MACH/MACL accumulator pair. Delay-slot execution is handled via a pending state (dly_active / dly_tgt) checked at the top of sh2_step(). Instruction set coverage:

MOV variants (immediate, register, @Rn, @Rm+, @-Rn, @disp)
ADD / SUB / AND / OR / XOR / NOT
CMP/EQ / CMP/GE / CMP/GT
DT (decrement and test)
SHLL / SHLR family
BRA / BSR / BT / BF with delay-slot forms
STS / LDS PR (procedure register save/restore)
TRAPA (treated as NOP)

Saturn bus seam (`cores/saturn.sg`)

saturn.sg is linked BEFORE sh2.sg so its bus overrides win under the first-def-wins link model. Memory layout:

512 KB boot ROM
2 MB work RAM-L at $06000000
2 KB VDP2 register shadow at $05E00000

sat_backdrop_argb() reads an RGB555 value from VDP2 offset $E0 and converts to ARGB. sat_render() fills the 320×224 framebuffer with the backdrop color. The emulation runs 47,633 SH-2 steps per frame.

uart=50 PASS. apps/saturn (25,880 B, arm-el0), loads /roms/game.bin (512 KB cap).

Sega 32X — system #44

Commit 8400f43. The 32X reuses sh2.sg with its own bus seam — the first demonstration of the SH-2 core serving two distinct systems.

32X bus seam (`cores/s32x.sg`)

s32x.sg is linked BEFORE sh2.sg, overriding the bus with the 32X memory map:

64 KB boot ROM at $00000000
256 KB WRAM at $06000000
320×224 frame VRAM at $04000000–$04022FFF (143,360 bytes, packed RGB555 big-endian)

s32x_rgb555() unpacks a 16-bit word: bits [14:10] → R, [9:5] → G, [4:0] → B → ARGB. s32x_render() blits 71,680 pixels from FVRAM to the ARGB framebuffer. The emulation runs 38,333 SH-2 steps per frame.

uart=51 PASS. apps/s32x (25,856 B, arm-el0), loads /roms/game.32x (64 KB cap).

The SH-2 pattern: one CPU, two systems

Saturn and 32X both use the SH-2 CPU without duplicating a line of CPU code. The bus seam is linked first; sh2.sg stubs are overridden via first-def-wins. Each system gets its own memory map, its own render path, and its own ROM cap — but the instruction decoder, register file, and delay-slot logic live exactly once.

sh2.sg          ← shared CPU: decode, registers, delay-slot
  ▲                ▲
saturn.sg       s32x.sg    ← per-system bus seams (linked first)
  │                │
sat_render()    s32x_render()  ← per-system framebuffer fill

This pattern will extend to any future SH-2 system (SH-2 variants appear in several Sega and Hitachi platforms) with the same zero-duplication guarantee.

Batch summary

#	System	CPU	Commit	uart	Size
41	Atari 800	6502A + GTIA	`2bc19e0`	48	38,560 B
42	MSX Turbo-R	R800 (Z80-compat)	`521c058`	49	52,944 B
43	Sega Saturn	SH-2 + VDP2	`31fc8c9`	50	25,880 B
44	Sega 32X	SH-2 + FVRAM	`8400f43`	51	25,856 B