Three landings that together close the x86 real-silicon peripheral stack: lcars_boot_banner draws a full-screen LCARS boot splash on the GOP framebuffer (orange top band + "SIGIL" in gold via lcars_gch_cov + tan accent), the NS16550A UART driver (COM1, SCR probe, baud divisor, 8N1 LCR, FIFO enable, loopback echo, CLS_SERIAL), and the Intel 8259A PIC master/slave cascade (IMR round-trip, ISR/IRR probe, IRQ1 mask/unmask, non-specific EOI, CLS_IRQ). With PIT + i8042 + RTC already shipped, the x86 port-I/O driver set is now complete for real-hardware bring-up. (sigil-video 9684cde; sigil-drivers 9fb80cd, 213ff01)
lcars_boot_banner (9684cde) — GOP framebuffer boot splash
This is the first thing a user sees when sigilOS boots on real x86 hardware. The banner fires after GOP maps the framebuffer and before the Lumen desktop compositor takes over.
lcars_boot_banner(fb, pitch, fbw, fbh, bh) — called once after GOP framebuffer is mapped, before kernel hands off to Lumen.
Layout (vertically stacked, full-width):
bh pixels tall, full width, lcars_orange(). The LCARS signature stripe.2×bh pixels tall, black background, holds "SIGIL" (5 chars) in lcars_gold() via lcars_gch_cov (the AA cov_blend path).bh/2 pixels tall, full width, lcars_tan(). Accent band beneath the text.GPU path: gpu_submit rect-fill (CAP_ACCEL; silicon-pending). SW path: lcars_fill_rect fill_span rows — the Pi3-floor fallback.
Test (160×120, bh=16): top band=orange, bottom band=tan, center=black, gold glyph pixel lit, pixel above top band=clear.
LCARS-BOOT-PASS top=ok bot=ok center=ok glyph=ok clear=okNS16550A UART (9fb80cd — sigil-drivers) — COM1 serial driver
Ports: base 0x3F8. Register map: RBR/THR (0), IER (1), IIR/FCR (2), LCR (3), MCR (4), LSR (5), MSR (6), SCR (7).
Full init sequence: IER disable → set DLAB → write baud divisor → clear DLAB → 8N1 LCR → FCR FIFO enable+clear (0xC7) → MCR DTR+RTS.
Live QEMU verified:
- SCR round-trip: write
0xA5→ read back0xA5. - Baud divisor at 115200: DLL=1, DLH=0 read-back confirmed.
- LSR THRE=1 (transmitter holding register empty — ready to send).
- MCR loopback: write
0x41('A') → read0x41.
CLS_SERIAL dispatcher: OP_INIT / PROBE / READ / WRITE / CTL_FLUSH / CTL_BAUD. State at 0x850000.
Intel 8259A PIC (213ff01 — sigil-drivers) — master/slave cascade
Two 8259A chips in cascade: master at 0x20/0x21, slave at 0xA0/0xA1. ICW1-4 initialization remaps master vectors to INT32, slave to INT40.
Live QEMU verified:
- IMR AA/55 round-trip (write bitmask, read back).
- ISR=0 (no IRQ currently in service).
- IRQ1 (keyboard) mask/unmask cycle.
- Post-init IMR=0xFF (all IRQs masked — safe default).
pic_mask / pic_unmask via power-of-2 loop (no bitwise — consistent with drivers convention). Non-specific EOI: 0x20 to master, 0xA0 to slave.
CLS_IRQ dispatcher: CTL_IRQ_MASK / UNMASK / EOI / READ_ISR / READ_IRR. State at 0x840000.
The complete x86 port-I/O driver set
With PIT + i8042 + RTC previously shipped and PIC + UART landing now, every port-I/O peripheral required for a real-hardware x86 boot path is wired. Together with the GOP framebuffer (MMIO), the LCARS boot banner, and apple_secboot chain-of-trust, the sigil-os#18 x86 real-hardware boot path has all required peripheral drivers.
| Driver | Ports | Class | PASS |
|---|---|---|---|
| MC146818A RTC | 0x70/0x71 | CLS_TIME | ✓ |
| Intel 8042 PS/2 | 0x60/0x64 | CLS_INPUT | ✓ |
| Intel 8253/8254 PIT | 0x40–0x43 | CLS_TIME | ✓ |
| Intel 8259A PIC | 0x20/0x21, 0xA0/0xA1 | CLS_IRQ | ✓ |
| NS16550A UART | 0x3F8 | CLS_SERIAL | ✓ |