HAL Batch 8 — SEP Mailbox/AltiVec/Thermal/XMON + SPMI/FPU (sigil-kernel a95edda→85d7a5a)

SEP coprocessor mailbox transport. The SEP (Secure Enclave Processor) is Apple Silicon's dedicated security coprocessor — it handles biometric templates, crypto keys, and secure boot material, all isolated from the AP (Application Processor). sep_chan_init(): initialises the SEP mailbox; sets chan_up=1 (channel established). sep_chan_send(endpoint, msg_type, payload): sends a TX message to the SEP. Each message is addressed by endpoint (0–255, where endpoint×256 encodes the target service) plus a msg_type (0–255 command selector) and a 32-bit payload. Increments tx_count. sep_chan_recv(endpoint): simulates a SEP→AP RX reply — returns a synthetic response for the endpoint. Increments rx_count. sep_chan_online(): returns 1 if chan_up is set. Note on bug fixed: the original avec_owner() == 0 - 1 sentinel comparison (intended to detect "no owner" = 0xFFFFFFFF) failed because cc0 peek32 returns stored 0xFFFFFFFF as unsigned, making the signed sentinel comparison unreliable. Fixed by using an msr_vec==0 init check instead. SEP init=1 snd=1 rcv=1 K.

G4/G5 AltiVec (VMX) context save/restore. AltiVec (VMX on G5) is the SIMD extension on G4/G5 PowerPC — 128-bit vector registers, used for DSP, audio, and video processing. The kernel implements lazy context switching: MSR[VEC] is disabled for all tasks by default; on first SIMD instruction, a "vector unavailable" trap fires, and the kernel grants the task its VEC context. altivec_trap_unavail(task): grants VEC to task; sets msr_vec=1 (enables AltiVec for the task). altivec_save(task): saves AltiVec context — captures VRSAVE (which VRs are live), VSCR (saturation/non-Java mode), and VR0 proxy value; sets ctx_dirty=0 (context is clean after save); clears msr_vec=0 (disables VEC). altivec_restore(task): restores AltiVec context from saved state; sets msr_vec=1. altivec_save_count() / altivec_restore_count() / altivec_trap_count(): telemetry counters. AVC init=1 sav=1 rst=1 K.

M-series 5-zone thermal manager. M-series SoCs have 5 independently monitored thermal zones: CPU-E (efficiency cores), CPU-P (performance cores), GPU, SSD, and Battery. therm_init(): zeros all zone temperatures and counters. therm_set_temp(zone, temp_c100): sets the temperature for zone zone (0=CPU-E, 1=CPU-P, 2=GPU, 3=SSD, 4=Battery) in units of °C×100 (e.g., 7500 = 75.00°C). therm_hottest_zone(): scans all 5 zones and returns the index of the highest temperature. therm_should_throttle(): returns 1 if any zone temperature ≥ 95.00°C (i.e., temp_c100 ≥ 9500). therm_should_shutdown(): returns 1 if any zone temperature ≥ 110.00°C (10999 in temp_c100 is safe; 11000 = 110.00°C triggers shutdown). therm_throttle_count(): returns number of throttle events observed. THM init=1 hot=1 thr=1 K.

PowerMac XMON kernel debugger interface. XMON is the built-in kernel debugger on PowerPC Linux/Macs — a minimal breakpoint + exception inspector that can be entered from the kernel panic handler or a hardware breakpoint. xmon_init(): initialises the 4-slot breakpoint table and clears IN_XMON gate. xmon_bp_add(addr): adds a breakpoint at addr to the first free slot in the 4-slot table. xmon_bp_remove(addr): removes a breakpoint from the table. xmon_exception_enter(exctype, excaddr, nip): records an exception entry — exctype (DSI=1 data-storage interrupt, ISI=2 instruction-storage interrupt, MCHK=3 machine-check, BRK=4 breakpoint), excaddr (the faulting address), nip (next instruction pointer = PC at exception entry). Sets in_xmon=1. xmon_in_xmon(): returns 1 while the debugger is active. xmon_exit(resume_pc): clears in_xmon; sets resume_nip=resume_pc (the PC at which the kernel resumes). XMN init=1 brk=1 exc=1 K.

SPMI bus master (PMU/thermal/USB-C PD). SPMI (System Power Management Interface) is a low-speed serial bus on M-series SoCs connecting the AP to slave devices: the main PMU (power management unit), thermal sensors, and USB-C Power Delivery controller. Each slave has a USID (Unique Slave ID, 0–15). spmi_init(): zeros the probe bitmask and counters. spmi_probe_slave(usid): probes for a slave at usid; sets bit usid in probe_mask. spmi_slave_present(usid): returns 1 if bit usid is set in probe_mask. spmi_write_ext(usid, addr, data): issues a WRITE-EXT command (extended address, for peripheral register space > 256 bytes). Sets spmi_busy=1 during transfer; clears on completion. Increments tx_count. spmi_read_ext(usid, addr): issues a READ-EXT command; returns (usid*16 + addr%16) as the synthetic read data. Increments rx_count. SPI init=1 prb=1 rw=1 K.

G3/G4/G5 FPU context save/restore (FPR0-31 + FPSCR). The G3/G4/G5 FPU has 32 64-bit floating-point registers (FPR0-FPR31) plus the FPSCR (Floating-Point Status and Control Register). Like AltiVec, the kernel uses lazy FPU context switching via MSR[FP]. fpu_trap_unavail(task): grants FP to task; sets msr_fp=1. fpu_save(task): saves FPU context — captures FPSCR snapshot and FPR0-1 proxy values; sets ctx_dirty=0; clears msr_fp=0. fpu_restore(task): restores FPSCR + FPRs; sets msr_fp=1. fpu_save_count() / fpu_restore_count() / fpu_trap_count(): telemetry counters. Design mirrors ppc_altivec_ctx.sg — the same MSR[FP] lazy-save pattern, ensuring consistency between FPU and SIMD context switching. FPU init=1 sav=1 rst=1 K.