sigil-kernel c2f25bc adds two HAL seams at 0x4E0000–0x4E1000: apple_display_pipe.sg wraps the M-series Display Coprocessor (DCP) — the autonomous display controller that drives all Apple Silicon laptop and desktop panels — and ppc_mesh.sg models the G3 Mesh / G4 HIO host interconnect that connects peripheral ASICs (Heathrow, K2, UniNorth) to the CPU on classic Power Macs.
apple_display_pipe.sg (0x4E0000) — DCP display coprocessor
Mode config, framebuffer, VSYNC
The DCP (Display Coprocessor, also DCPAV on some M-series variants) is an autonomous coprocessor that handles all display timing, scaling, and color management on Apple Silicon Macs.
dcp_init(): probes the DCP controller; marks init complete. dcp_mode_set(w, h, hz, bpp): configures display mode — width, height, refresh rate (Hz), and bits-per-pixel (16 or 32). dcp_fb_set(addr): sets the framebuffer base address (physical). dcp_vsync_count(): returns the VSYNC interrupt counter (increments once per frame; used for frame pacing). dcp_brightness_set(pct): sets display brightness 0–100 (maps to PWM duty cycle via DCP firmware). DCP init=1 mod=1 hdr=1 K.HDR — P3 / BT.2020 color space + peak nits
dcp_hdr_enable(color_space, peak_nits): enables HDR mode. color_space: 0=sRGB (default), 1=Display P3 (DCI-P3 primaries, D65 white, used on all Apple displays since 2016), 2=BT.2020 (wide color for Pro Display XDR). peak_nits: maximum display luminance in cd/m² (e.g. 600 for MacBook Pro, 1600 for Pro Display XDR XG). dcp_hdr_active(): returns 1 if HDR is engaged. dcp_color_space(): returns the active color space index. HDR is initialized off; dcp_hdr_enable is called by the color profile subsystem when HDR content is detected.ppc_mesh.sg (0x4E1000) — G3 Mesh / G4 HIO host interconnect
Sync/reset state machine + peripheral probe
The Mesh bus (G3 Power Mac) and HIO bus (G4 Power Mac) are the host interconnects that bridge the CPU to peripheral ASICs (Heathrow on G3, K2 and UniNorth on G4).
mesh_init(variant): sets the bus variant — 0=Mesh (G3), 1=HIO (G4). mesh_sync(): issues a bus sync; sets mesh_synced=1. mesh_reset(): resets the bus; clears sync flag; increments reset counter. mesh_reset_count(): returns total resets. mesh_bus_width(): returns bus width in bits (32 for Mesh, 64 for G4 HIO).Peripheral ASIC probe bitmask
mesh_probe_asic(id): probes for a peripheral ASIC on the bus. id encodes the ASIC type: 0=Heathrow (G3 I/O ASIC — USB, IDE, SCSI, sound), 1=K2 (G4 I/O ASIC — FireWire, USB 2.0, ATA), 2=UniNorth (G3/G4 North Bridge). Sets bit id in mesh_probe_mask if probed. mesh_probe_mask(): returns the bitmask of probed ASICs. mesh_hio_variant(): returns 1 if the bus is G4 HIO mode. MSH init=1 prb=1 rst=1 K.Arch matrix now at 0x4E1000. Batch 7 extends the display and bus tier: the DCP seam is the kernel handle for all M-series display output (including HDR/P3), and the Mesh/HIO seam models the classic PowerPC peripheral bus that ties SCSI, USB, FireWire, and ATA controllers to the CPU.