Four more sigil-kernel commits push the arch matrix from 0x4BE000 to 0x4C5000, adding 8 HAL seams across the Apple Silicon and PowerPC families: NVMe host queue, VIA-CUDA ADB/PMU coordinator, SEP mailbox, G4/G5 L3 cache, T8103 PCIe host controller, PPC XMON debugger register save, CPMU performance counters, and G4/G5 thermal management. All pass QEMU INIT tests.
9dd3307 — NVMe + VIA-CUDA
apple_nvme.sg
(0x4BE000)
(0x4BE000)
ANS2/ANS3 NVMe host queue. 8-slot submission/completion ring.
nvme_submit(lba, len, buf, is_write): finds a free slot, writes NVMe SQE (opcode/nsid/LBA/len/buf), advances the tail pointer, rings the doorbell register. nvme_complete(): checks the CQ phase bit; on completion, reads status, records ERR_LBA if status non-zero, advances CQ head. nvme_poll(): calls nvme_complete() in a spin loop until the expected tag completes or the queue drains. Queue-full guard: if all 8 slots are occupied, submit returns NVM_ERR_FULL. NVM init=1 sub=1 cmp=1 K.ppc_via_cuda.sg
(0x4BF000)
(0x4BF000)
VIA-CUDA ADB/PMU/PRAM coordinator. VIA-CUDA is the ADB bus + power management coordinator on NuBus/PCI Power Macs (G3/G4).
via_adb_inject(addr, cmd, data): writes a 3-byte ADB packet to the CUDA transmit buffer (addr 2 = keyboard, addr 3 = mouse). via_adb_poll(buf): reads ADB response from receive buffer. via_pram_read(offset): reads a byte from PRAM (parameter RAM) at the given offset via CUDA command 0x20. via_pram_write(offset, val): writes PRAM byte. via_pmu_cmd(cmd): sends a PMU command (e.g., 0xEC = sleep). via_rtc_read(): reads Mac-epoch RTC (seconds since Jan 1 1904) as u32. VIA init=1 adb=1 pmu=1 K.139a49b — SEP + G4/G5 L3 cache
apple_sep.sg
(0x4C0000)
(0x4C0000)
Secure Enclave Processor mailbox. The SEP is Apple Silicon's isolated security co-processor — handles Touch ID, Face ID, device keys, and boot manifest verification.
sep_init(): sends INIT command via SEP mailbox; waits for ACK; sets boot manifest gate. sep_request(req_type, key_slot): writes a crypto request (type + key slot index) to the SEP request FIFO. sep_complete(): polls SEP response FIFO; reads result status + output key material. sep_key_alloc(slot): sets bit in 32-slot key bitmask; returns the slot. sep_key_free(slot): clears bit. sep_nonce_roll(): advances the rolling nonce counter (used for freshness in crypto requests). sep_lock(): seals the key store — further key_alloc calls return SEP_ERR_LOCKED. SEP init=1 req=1 key=1 K.ppc_l3cache.sg
(0x4C1000)
(0x4C1000)
G4 7450 + G5 970MP L3 controller.
l3c_init(variant): selects G4 or G5 preset. G4 preset: 1MB, 8-way set-associative, 64B cache lines, ECC enabled. G5 preset: 512KB, 8-way, 128B lines, ECC enabled. l3c_enable() / l3c_disable(): toggles L3 unit (writes L3CR bit on G4, L3CR2 on G5). l3c_flush(): issues a global L3 flush (writeback + invalidate). l3c_hit_stat() / l3c_miss_stat(): read hit/miss counters from the L3 performance monitor registers. l3c_hit_rate(): returns integer hit-rate percentage = hits × 100 / (hits + misses). L3C init=1 cfg=1 hit=1 K.1e11886 — T8103 PCIe + PPC XMON
apple_t8103_pcie.sg
(0x4C2000)
(0x4C2000)
M1 T8103 4-port PCIe host controller. The T8103 (M1) has a custom PCIe host controller with 4 root ports. Per-port descriptor:
vendor:u16, device:u16, class:u8, bar0:u32, speed:u8 (Gen1–Gen4), width:u8 (×1/×2/×4). pcie_attach(port, vendor, device, class, bar0, speed, width): writes port descriptor. pcie_detach(port): clears descriptor. pcie_active_count(): counts active ports. M1 preset via pcie_preset_m1(): port 0 = NVMe (vendor 0x106B, Gen4×4), port 1 = BCM4378 WiFi (vendor 0x14E4, Gen2×1). PCI init=1 dev=1 cnt=1 K.ppc_xmon.sg
(0x4C3000)
(0x4C3000)
PowerPC XMON NMI debugger register save. XMON is the built-in NMI kernel debugger on PPC Linux/Darwin. The seam provides a save area for all architectural registers at NMI entry.
xmon_enter(panic_code): saves GPR0–GPR31 (32×4B) and SPR set (MSR, LR, CTR, XER, CR, SRR0, SRR1, DAR, DSISR) via poke32 into the save area at XMON_BASE. Records panic_code. Sets xmon_active flag. xmon_backtrace(depth): records backtrace depth in the save area. xmon_exit(): clears xmon_active flag, zeroes save area. XMN init=1 ent=1 bt=1 K.e30ccf6 — CPMU + PPC Thermal
apple_cpmu.sg
(0x4C4000)
(0x4C4000)
CPU Performance Monitor Unit. 8 programmable event counters + 3 fixed counters (cycles, instructions, L2 refs).
cpmu_init(): zeroes all counters. cpmu_count(idx, event_code): configures programmable counter idx to count event_code (e.g., 0x02 = L1D miss, 0x05 = branch mispred). cpmu_read(idx): reads accumulated count for counter idx. cpmu_disable(idx): stops counter and resets. Disable-guards: cpmu_read on a disabled counter returns 0, not a stale value. cpmu_ipc(): fixed-counter IPC = instructions × 100 / cycles (integer, scaled ×100). PMU init=1 cnt=1 ipc=1 K.ppc_thermal.sg
(0x4C5000)
(0x4C5000)
G4/G5 thermal + fan/throttle.
thermal_init(variant): G4 preset (warn=70°C, crit=85°C) or G5 preset (warn=80°C, crit=95°C). thermal_fan_set(pct): sets fan speed 0–100% via PWM register. thermal_fan_interp(temp): linear interpolation from temperature to fan percentage: below warn → 20%, above crit → 100%, linear in between. thermal_throttle(temp): if temp ≥ crit, writes 50% clock multiplier to the throttle register. thermal_overheat(temp): returns 1 if temp ≥ crit + 10 (overheat shutdown threshold). THL init=1 fan=1 thr=1 K.Arch matrix summary
Arch matrix now at 0x4C5000. Running total: 28 HAL seams added in this batch series (0x4BA000–0x4C5000 = 12 addresses × 2 seams each).
| Commit | Seam A | Seam B | Family |
|---|---|---|---|
9dd3307 | apple_nvme.sg (0x4BE000) | ppc_via_cuda.sg (0x4BF000) | Apple Silicon / PPC G3/G4 |
139a49b | apple_sep.sg (0x4C0000) | ppc_l3cache.sg (0x4C1000) | Apple Silicon / PPC G4/G5 |
1e11886 | apple_t8103_pcie.sg (0x4C2000) | ppc_xmon.sg (0x4C3000) | Apple M1 / PPC |
e30ccf6 | apple_cpmu.sg (0x4C4000) | ppc_thermal.sg (0x4C5000) | Apple Silicon / PPC G4/G5 |