HAL Batch — Apple ANE/DART IOMMU + PPC AltiVec/HyperTransport Seams (sigil-kernel c7128c6 + 36a1581)

Two sigil-kernel commits (c7128c6, 36a1581) add four new HAL seams, extending the arch matrix to 0x4BD000: Apple Neural Engine (ANE, M1–M4) at 0x4BA000, PPC AltiVec (G4/G5 VMX SIMD) at 0x4BB000, Apple DART IOMMU at 0x4BC000, and G5 HyperTransport bus topology at 0x4BD000. All four pass QEMU INIT tests; silicon gated.

c7128c6 — Apple ANE + PPC AltiVec

apple_ane.sg (0x4BA000)

M-series Neural Engine (M1–M4). 7 inference slots × 16B per slot. ane_init(): zeroes all slots, sets TFLOPS from chip gen param (M1=11.6, M2=15.8, M4=25.6 as fixed-point ×10). ane_power_on/off(slot): marks slot active/inactive in the slot table. ane_slot_alloc(size_mb): finds first free slot, records size_mb; returns slot index. ane_slot_done(slot): marks slot idle (inference complete). ane_slot_release(slot): zeroes slot entry (frees allocation). Caps-gated on CAP_ANE — the ANE seam can only be called by a process holding the neural-engine capability. M1 has 7 Physical Partition Clusters, matched by the 7-slot table. TFLOPS is parameterized so the same code path serves M1 through M4. ANE init=1 pwr=1 slt=1 K.

ppc_altivec.sg (0x4BB000)

G4/G5 AltiVec (VMX) SIMD. altivec_enable(): sets MSR[VEC] bit (bit 25) to enable the VMX unit. altivec_save(ctx): saves VR0–VR31 (32 vector registers × 16B each = 512B) + VRSAVE (4B) + VSCR (4B) to context buffer at ctx. altivec_restore(ctx): loads VR0–VR31 + VRSAVE + VSCR from ctx. All register save/restore uses poke8 at fixed offsets. Caps-gated: altivec_enable() checks the ALTIVEC bit from ppc_soc_cfg(socc_caps()) — if the SOC doesn't report AltiVec capability, enable is a no-op (G3 floor stays safe). AVX init=1 enb=1 sav=1 K.

36a1581 — Apple DART IOMMU + G5 HyperTransport

apple_dart.sg (0x4BC000)

DART per-device IOMMU. 16-entry page table (16 devices × 8B each). Each entry: dva:u32 (device virtual address) + paddr:u32 (physical address). dart_map(dev, dva, paddr): writes entry at dev index. dart_bypass(dev): sets entry to bypass mode (dva=paddr=0xFFFFFFFF sentinel). dart_tlb_flush(): writes flush register (DART_FLUSH constant) to trigger hardware TLB invalidation. dart_fault(): reads DART_ERR_ADDR and DART_SID registers, returns last fault address and source ID for diagnostics. DART is Apple's per-device IOMMU (Device Address Resolution Table). Each PCIe or USB device attached to M1/M2/M4 SoC has its own DART instance; the sigilOS seam abstracts one device's DART. DRT init=1 map=1 byp=1 K.

ppc_htype.sg (0x4BD000)

G5 HyperTransport bus topology. 4-link table (4 × 16B each): speed_mhz:u16, width_bits:u8, partner_node:u8, flags:u32, reserved. htype_init(): zeroes all links. htype_set_link(n, speed, width, partner): writes link descriptor. htype_preset_g5(): applies IBM G5 preset — link 0 = North Bridge (1000 MHz, 16-bit), link 1 = South Bridge (600 MHz, 8-bit), links 2–3 cleared. htype_preset_xserve(): Xserve variant — link 0 = 900 MHz/16-bit. htype_bw_total(): computes total unidirectional bandwidth = Σ (speed × width / 8) across active links; returns GB/s × 1000 as integer. G5 preset: 2000 MB/s (NB) + 600 MB/s (SB) = 2600 MB/s. HTP init=1 lnk=1 bw=1 K.

Arch matrix after this batch

Address	Seam	Commit	Status
`0x4BA000`	`apple_ane.sg` — M1–M4 Neural Engine	`c7128c6`	QEMU PASS · silicon gated
`0x4BB000`	`ppc_altivec.sg` — G4/G5 VMX SIMD	`c7128c6`	QEMU PASS · silicon gated
`0x4BC000`	`apple_dart.sg` — DART IOMMU	`36a1581`	QEMU PASS · silicon gated
`0x4BD000`	`ppc_htype.sg` — G5 HyperTransport	`36a1581`	QEMU PASS · silicon gated

The ANE and DART seams pair naturally: when the ANE seam allocates an inference slot it will eventually need DART mappings to give the neural engine DMA access to model weights in physical memory. The DART seam provides the per-device IOMMU plumbing for that path. They ship in separate commits here because the IOMMU mapping protocol depends on silicon specifics still being characterized; the seams are structurally ready to compose once that work lands.

On the PPC side, AltiVec and HyperTransport address separate layers of the G4/G5 stack. AltiVec is a CPU feature (context-save for the VMX unit); HyperTransport describes the bus topology connecting CPU to memory and I/O bridges. Both are needed for a complete G5 port and both pass INIT tests clean. The htype_bw_total() helper gives the scheduler visibility into aggregate bus bandwidth — useful when deciding whether to route a workload through the AltiVec unit or fall back to scalar.