ISA Legacy Complete: Intel 82077AA FDC + PC Parallel Port LPT1 — 10 Drivers, Full x86 Legacy Stack

The x86 ISA legacy driver set is complete: Intel 82077AA Floppy Disk Controller (FDC) and PC parallel port LPT1 join the stack, bringing the total to 10 verified x86 drivers (12 counting the two new ones — all verified together). Every major IBM PC-AT era device now has a live-QEMU-verified CLS-dispatched driver. (sigil-drivers 1629535, a018249)

sigilOS desktop — Lumen file manager — sigilOS desktop — full x86 ISA legacy driver stack complete

Intel 82077AA FDC (1629535) — drivers/storage/fdc

The Intel 82077AA is the canonical ISA floppy disk controller, present in virtually every PC from the mid-1980s through the early 2000s. It is also present in QEMU's default x86 machine, making it an important target for the legacy stack — an uninitialized FDC causes BIOS stalls on drive enumeration even when no floppy is attached.

I/O port map

DOR (0x3F2)

Digital Output Register: motor control (bits 4–7), drive select (bits 0–1), DMA enable (bit 3), reset (bit 2 active-high deassert).

MSR (0x3F4)

Main Status Register (read-only): RQM (bit7 = Request for Master, controller ready to transfer) and DIO (bit6 = data direction, 1=controller→CPU).

FIFO (0x3F5)

Data FIFO: command byte stream in, result byte stream out. Direction determined by DIO bit in MSR.

CCR (0x3F7)

Configuration Control Register (write-only): data rate. Rate=0 = 500kbps (double-density MFM standard).

Reset sequence

The reset sequence follows the 82077AA spec exactly. DOR=0x00 asserts hardware reset; DOR=0x0C deasserts it (drive 0 selected, DMA enabled). After reset, the controller asserts interrupts for each drive in the system — these must be drained by issuing 4× SENSE_INTERRUPT (command 0x08) before any other command. Live QEMU result: ST0=0xC3 (drive 3 ready-changed), PCN=0 on each SENSE_INT — correct per spec for a system with no floppy inserted.

SPECIFY command

Command 0x03/0xCF/0x02 sets head load time, step rate, and DMA mode. The 82077AA accepts SPECIFY silently — no result bytes are returned, which is correct per the datasheet. The driver verifies acceptance by confirming MSR returns to RQM=1 after the three command bytes are written.

Driver internals

fdc_wait_rqm: polls MSR bit7 in a spin loop — the controller must be ready before each byte transfer.
fdc_wait_result: reads result bytes from the FIFO with a 5M-iteration timeout — used after commands that return status bytes.
CLS_STORAGE dispatcher: OP_PROBE / OP_INIT / CTL_RESET. State at 0x8D0000.

Practical note: The FDC is required for booting from floppy on early x86 boards — the BIOS calls INT 0x13 functions (which sigilOS will eventually reroute) to read the boot sector. Even in QEMU, having a properly initialized FDC ensures the firmware does not stall on legacy drive enumeration at boot. This is why the FDC driver ships before any floppy filesystem support.

PC Parallel Port LPT1 (a018249) — drivers/char/lpt

LPT1 at I/O ports 0x378–0x37A. The parallel port predates USB by two decades and remains a useful general-purpose 8-bit I/O bus. In sigilOS it is not a printing interface — it is a GPIO-level hardware bus for JTAG adapters, logic analyzers, and legacy test equipment. CLS_CHAR dispatcher. State at 0x8E0000.

Register map

DATA (0x378)

Bidirectional 8-bit data bus. Read/write verified with patterns 0xA5 and 0x5A in lpt_probe.

STATUS (0x379)

Read-only status lines: nBUSY (bit7, inverted), nACK (bit6), PAPER-END (bit5), SELECT (bit4), nERROR (bit3). Live QEMU STATUS = 0xD9.

CONTROL (0x37A)

STROBE (bit0), AUTO-LF (bit1), nINIT (bit2), SELECT-IN (bit3), IRQ-ENABLE (bit4), BIDIR (bit5). Bits 7:6 are stuck=1 in QEMU — hardware artifact; verification masks with % 64 == 12.

Driver operations

lpt_probe: DATA round-trip test — write 0xA5, read back. Confirms the port is present and bidirectional data works.
lpt_strobe: asserts STROBE (bit0) then deasserts — triggers a data latch on attached printers or external devices.
lpt_bidir_on / lpt_bidir_off: set/clear CONTROL bit5. With BIDIR on, the port becomes an 8-bit input bus — the DATA register reads external signal levels rather than driving them. This is the mode used for JTAG and logic capture.
Init sequence: writes CONTROL=12 (nINIT=1, SELECT_IN=1) to deassert reset and assert printer select. This is the standard power-on state for any attached device.

Practical note: The BIDIR mode (bit5) is especially useful beyond printing. With bit5 set, LPT1 becomes an 8-bit input port — a standard interface for inexpensive JTAG adapters (Wiggler, ByteBlaster) and legacy oscilloscope interfaces. sigilOS uses this mode to support hardware debugging without a dedicated JTAG controller.

Complete x86 driver inventory — all 12 verified

All drivers verified on live QEMU via x86-runverify:

Driver	I/O Ports	CLS Class	State Address
Intel 8253/8254 PIT	`0x40–0x43`	CLS_TIME	`0x820000`
Intel 8259A PIC	`0x20 + 0xA0`	CLS_IRQ	`0x830000`
Intel 8237A DMA	`0x00–0x0F`	CLS_DMA	`0x840000`
NS16550A UART COM1	`0x3F8`	CLS_SERIAL	`0x850000`
PS/2 i8042	`0x60 + 0x64`	CLS_INPUT	`0x860000`
MC146818A RTC	`0x70 + 0x71`	CLS_TIME	`0x870000`
PCI Config Space	`0xCF8 + 0xCFC`	CLS_BUS_PCI	`0x880000`
Bochs BGA	`0x1CE + 0x1CF`	CLS_DISPLAY	`0x890000`
QEMU fw-cfg	`0x510 + 0x511`	CLS_PLATFORM	`0x8A0000`
PC Speaker	`0x61`	CLS_AUDIO	`0x8C0000`
Intel 82077AA FDC	`0x3F0–0x3F7`	CLS_STORAGE	`0x8D0000`
PC Parallel LPT1	`0x378–0x37A`	CLS_CHAR	`0x8E0000`

Every IBM PC-AT era device class is now represented: timers, interrupt controller, DMA, serial, input, RTC, PCI bus, display, platform config, audio, storage, and character I/O. The x86 ISA legacy layer is complete.