Apple Silicon HAL Batch 6: BT 5.x, ChipID, DART2 IOMMU, Ethernet + PowerPC FPU, MCE, Decrementer

sigil-kernel's sixth HAL batch wires 9 more components — Apple: Bluetooth 5.x seam (BCM4387, LE scan/peer-inject/connect), ChipID fuse (M1/M1Pro/M2 identity, cores/GPU/media engines/RAM, chip_is_pro()), DART2 IOMMU (8-entry VA→PA map ring, TLB flush, fault-inject), Ethernet dual-class (BCM57762 1GbE + AQC107 10GbE, TX counter + RX frame inject), SPI NOR flash (64-word page, CRC word-sum, erase/restore). PowerPC: G5 970/970MP 8-counter PMU (ppc_g5perf, INSTR/CYCLES/L1D-miss event codes, IPC×100), Machine Check Exception handler (MCSR L2_ECC/L2_MBIT/EXTERNAL bits, recoverable vs fatal, 4-entry ring log), G3/G4/G5 FPU model (32 FPRs, FPSCR, fadd/fmul, zero-divide ZX exception), G3/G4/G5 Decrementer + Time Base (TBL/TBU bus÷4, countdown, underflow→pend+reload). All QEMU PASS. (sigil-kernel b22b32a, 4c2f9e6, 960ba70, 6a0cb9c)

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Apple Silicon — Batch 6

Five new M1 seams land in this batch, covering connectivity, identity, memory virtualization, networking, and storage.

apple_bt.sg — Bluetooth 5.x BCM4387 (b22b32a)

LE Bluetooth seam modeling the BCM4387 found in M1 Macs. Power/scan/peer-inject/connect flow: a 4-entry scan ring holds discovered peers; connect resolves peer-id 0 from the ring. MMIO base 0x445000.

PASS: BT init=1 en=1 scan=1 conn=1

apple_chipid.sg — Chip identity fuse (b22b32a)

Reads the silicon identity fuse: M1 (chip_id=0), M1 Pro (chip_id=1, 10 performance cores), M2 (chip_id=2, 8 GPU slices, 2 media engines). chip_is_pro() tests GPU count ≥ 14. RAM, core, GPU, and media-engine fields all addressable. MMIO base 0x446000.

PASS: CHIPID m1=1 pro=1 id=1

apple_dart2.sg — DART2 per-device IOMMU (4c2f9e6)

Models the DART2 IOMMU used to isolate DMA-capable peripherals on M1. Stream enable, 8-entry VA→PA map ring, lookup, unmap, TLB flush, and fault inject via DART2_FAULT_ADDR. MMIO base 0x448000.

PASS: DART2 init=1 map=1 umap=1 flt=1

apple_ethernet.sg — Dual-speed Ethernet (960ba70)

Dual-class seam covering both BCM57762 (1GbE, vendor 0x10DE) and AQC107 (10GbE, vendor 0x1FFF). Common interface: init+MAC set, set-speed, link-up, TX frame counter, RX inject/poll. MMIO base 0x44B000.

PASS: ETH init=1 spd=1 tx=1 rx=1

apple_spimem.sg — SPI NOR 64-word page (6a0cb9c)

SPI NOR flash model: 64-word page, init fills with 0xFF, program+read path computes CRC as a word-sum over all page words, erase restores the 0xFF blank state. MMIO base 0x44D000.

PASS: SPIMEM init=1 pgm=1 era=1

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PowerPC — Batch 6

Four new G3/G4/G5 seams extending the classic PowerPC HAL coverage into performance monitoring, exception handling, floating-point, and timekeeping.

ppc_g5perf.sg — G5 970/970MP 8-counter PMU (b22b32a)

Performance Monitor Unit for the 970 and 970MP cores. Eight hardware counters with INSTR, CYCLES, and L1D-miss event codes. Freeze/enable/inject controls. IPC×100 computed in fixed-point: (instr_count * 100) / cycle_count. MMIO base 0x447000.

PASS: G5PMU init=1 cfg=1 ipc=1

ppc_mce.sg — Machine Check Exception handler (4c2f9e6)

MCSR decode covering L2_ECC, L2_MBIT, and EXTERNAL fault bits. Recoverable vs fatal classification: recoverable errors log to a 4-entry ring; fatal errors set the halt flag. MMIO base 0x449000.

PASS: MCE init=1 rec=1 fat=1

ppc_fpu.sg — G3/G4/G5 FPU model (960ba70)

32 FPRs stored at ×1000 fixed-point scaling. FPSCR status register. fadd and fmul operations. Zero-divide ZX exception injection into FPSCR. MMIO base 0x44C000.

PASS: FPU init=1 add=1 mul=1 exc=1

ppc_dec.sg — G3/G4/G5 Decrementer + Time Base (6a0cb9c)

Decrementer countdown seam with MMIO reload register. Each tick decrements the counter; underflow sets pend and reloads. TBL/TBU registers increment at bus-clock÷4, giving the 64-bit time base. Interrupt ack clears the pending flag. MMIO base 0x44E000.

PASS: DEC init=1 tick=1 fire=1

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HAL cumulative count

Batch 6 brings the combined Apple Silicon + PowerPC HAL coverage past 55 components. The combined M1 + G3/G4/G5 seam set now spans the full compute, security, connectivity, memory, and I/O subsystems needed for real-silicon bring-up.

Batch	Apple seams	PowerPC seams	Batch total	Running total
Batch 1	8	0	8	8
Batch 2	4	0	4	12
Batch 3	8	6	14	26
Batch 4	6	4	10	36
Batch 5	6	4	10	46
Batch 6	5	4	9	55

Batch 6 closes out the connectivity tier (BT + Ethernet), the memory-virtualization tier (DART2), the silicon-identity tier (ChipID), and — on the PowerPC side — the floating-point, exception, performance, and timekeeping seams that are prerequisites for a real OS scheduler. The HAL is now dense enough that the next major step is exercising these seams from the kernel boot path rather than standalone QEMU harnesses.