Apple Silicon HAL Batch 4: Secure Boot, Media Engine, ProMotion VRR, MagSafe 3

Four commits, ten new HAL seams: sigil-kernel's fourth HAL batch completes the M1 bring-up surface with six Apple Silicon components and adds four more PowerPC G4/G5 seams. Every component passes QEMU. (473e0b7, 393806e, 834c69a, 2e339ba)

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HAL status

The M1 HAL is now complete for bring-up. Batch 4 lands 10 more components across Apple Silicon and PowerPC G3/G4/G5, closing out the subsystems needed before real-silicon work begins. Every seam follows the same pattern: a .sg driver stub, a fixed MMIO base, and a QEMU loopback test that exercises the full control flow.

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Apple Silicon — Batch 4

Six new M1 seams across 4 commits:

apple_secboot.sg (473e0b7)

4-stage chain-of-trust — BootROM → iBoot1 → iBoot2 → XNU. Three security levels: Full, Reduced, and Permissive. SIP flag tracked per-stage; per-stage fail injection for test coverage. MMIO base 0x439000.

PASS: SBOOT init=1 all=1 red=1

apple_wdog.sg (393806e)

SoC watchdog timer — 10s countdown at 24MHz reference clock. Enable/pet/tick-down sequence, RSTEN flag sets on expiry. MMIO base 0x438000.

PASS: WDOG init=1 en=1 tick=1 pet=1

apple_memc.sg (834c69a)

AMC unified memory controller — 8GB LPDDR4X at 4266MT/s, dual-channel. Per-client bandwidth throttle (CPU / GPU / ANE / ISP), page retire, ECC. MMIO base 0x436000.

PASS: MEMC init=1 bw=1 thr=1 ret=1

apple_media.sg (834c69a)

Media Engine — H264, HEVC, VP9, and ProRes encode sessions. 8-slot session pool, frame counter per session, caps bitmask. MMIO base 0x437000.

PASS: MEDIA init=1 sess=1 enc=1

apple_promo.sg (2e339ba)

ProMotion 10–120Hz VRR — content-adaptive rate selection (UI=10Hz, game=120Hz), LPM mode for always-on display, per-frame vsync counter. MMIO base 0x434000.

PASS: PROMO init=1 auto=1 lpm=1

apple_magsafe.sg (2e339ba)

MagSafe 3 — attach/negotiate/charge/full state machine. 29–96W range, MS3 vs USB-C type flag, 4800mA current at 96W. MMIO base 0x435000.

PASS: MSAFE init=1 att=1 det=1 full=1

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PowerPC — Batch 4

Four new G4/G5 seams closing out the classic Mac Pro HAL surface:

ppc_pcie.sg (473e0b7)

K2/SB600 PCIe bridge — x16 GPU slot (Radeon X800) plus two x1 expansion slots. Gen1 speed, AMD vendor ID 4098, empty-slot detection. MMIO base 0x43A000.

PASS: PPCIE init=1 gpu=1 x1=1

ppc_therm.sg (393806e)

G5 970FX/970MP thermal management — TRIP1 at 55°C kicks half-freq + fan=200; 78°C triggers throttle + fan=255 + min-freq; cool recovery path. MMIO base 0x429000.

PASS: GTHERM init=1 trip=1 thr=1 cool=1

ppc_ddr2.sg (834c69a)

G5 DDR2 controller (U3H) — 2GB dual-channel 533MT/s, CL4-4-4 timings. ECC enable and inject, self-refresh entry/exit. MMIO base 0x428000.

PASS: DDR2 init=1 sr=1 ecc=1

ppc_agp.sg (2e339ba)

G4/G5 AGP bridge (Uni-N2) — 4x/8x rate caps, 256MB GART page table, TLB flush. MMIO base 0x427000.

PASS: AGP init=1 rate=1 gart=1

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M1 HAL is complete

After four batches, every major M1 subsystem has a verified HAL seam. The full component list across all batches:

Batch	Components
1	AIC, boot, UART, MMU, PMGR, GPIO, DART, I2C, PCIe RC, SPI
2	ANS2 NVMe, FB, SEP, USB, BCM4387 WiFi, Thermal, NVRAM, GMAC, RTKit, ANE
3	audio, SMBus, blkdev, USB-PD, biometric, ISP, TB4
4	secboot, wdog, MEMC, Media Engine, ProMotion VRR, MagSafe 3

The next milestone is real-silicon bring-up: replacing QEMU loopback stubs with actual driver calls against M1 hardware. Each .sg seam already has the MMIO address, register layout, and control flow correct — the transition is wiring the seam outputs to real peripheral responses rather than the QEMU echo path. That work opens the 0.6.0 hardware sprint.