sigil-kernel's twentieth HAL batch adds 2 seams. Apple: apple_tb.sg — Thunderbolt/USB4 dual-port controller (2 ports, 40 Gbps, DisplayPort alt-mode, PCIe tunnel, 85W power source, connect/disconnect). PowerPC: ppc_keylargo.sg — G4 KeyLargo I/O hub (chipID=0x3C, feature gating for USB/FireWire/ATA, 2-channel ATA probe with master+slave device detection, 64-pin GPIO). Both QEMU PASS. ~142 HAL seams total. (sigil-kernel 7142fd9)
apple_tb.sg (7142fd9): Apple Thunderbolt/USB4 port controller
The apple_tb.sg seam models the Thunderbolt/USB4 port controller found on Apple Silicon Macs. It presents two ports and the full range of services those ports provide: high-speed data (USB4 Gen 3×2 / Thunderbolt 3/4 at 40 Gbps), video output (DisplayPort alt-mode), PCIe tunneling for docks and eGPUs, and USB Power Delivery as a power source.
tb_connect(port) marks the port as connected and initializes link negotiation. tb_disconnect(port) disconnects. Port state: TB_DISCONNECTED / TB_CONNECTING / TB_CONNECTED.tb_dp_enable(port) activates DisplayPort tunneling over the Thunderbolt link. Used when an external display is connected via USB-C/TB4.tb_pcie_enable(port) activates PCIe tunneling — allows Thunderbolt docks and eGPUs to present as PCIe devices to the host. The PCIe Root Complex (apple_pcie_rc.sg) can enumerate devices on a tunneled PCIe bus.tb_power_set(port, watts) sets the USB Power Delivery source output (0W = disabled, up to 85W = USB-PD 3.0 laptop charging). The port acts as a power source for connected devices.Base address: 0x4B3000. PASS: TB init=1 con=1 tun=1
ppc_keylargo.sg (7142fd9): G4 KeyLargo I/O hub
KeyLargo is the south-bridge / I/O hub on the Power Mac G4 (AGP and later) and PowerBook G4 Ti. It's the chip that manages all the "slow" I/O: USB, FireWire, ATA disk, and GPIO for the front-panel buttons and indicators. The ppc_keylargo.sg seam models its initialization, feature gating, ATA enumeration, and GPIO.
keylargo_enable(feat) / keylargo_disable(feat) individually enable or disable subsystems. Features: FEAT_USB (USB 1.1 controller), FEAT_FW (FireWire 1394a controller), FEAT_ATA (Ultra ATA/66 disk controller). Feature gating is how the OS turns off unused subsystems to save power.keylargo_ata_probe(ch) probes ATA channel ch (0 = internal hard disk, 1 = optical drive / zip). Returns: ATA_MASTER_ONLY if only the master device responds, ATA_BOTH if master and slave both respond, ATA_NONE if no device. This is the bus enumeration step the OS performs on boot.keylargo_gpio_write(pin, val) / keylargo_gpio_read(pin) — 64 GPIO pins controlling front-panel power LED, hard disk LED, power button interrupt, speaker, and more.Base address: 0x4B4000. PASS: KLG init=1 ata=1 gpio=1
Batch 20 seam table — 0x4B3000–0x4B4000
| Base address | File | Description | Status |
|---|---|---|---|
0x4B3000 | apple_tb.sg | Thunderbolt/USB4 dual-port controller — 2×40 Gbps, DP alt-mode, PCIe tunnel, 85W PD source | PASS |
0x4B4000 | ppc_keylargo.sg | G4 KeyLargo I/O hub — chipID=0x3C, USB/FW/ATA feature gating, 2-ch ATA probe, 64-pin GPIO | PASS |
Batch 20 brings the total HAL seam count to approximately 142, spanning Apple Silicon, Intel x86, PowerPC, ARM/Raspberry Pi, and RISC-V targets. The NIC driver ABI established in nic_iface.sg (see SRDX transport post) is the next link in the hardware abstraction chain — apple_tb.sg's PCIe tunnel surface will eventually expose the e1000 NIC on Thunderbolt docks through that same contract.