Apple Silicon HAL Batch 19: DMA, SIO, SEP + PPC VIA Timer, Cuda, G4 UniNorth

sigil-kernel's nineteenth HAL batch adds 6 more seams. Apple Silicon: M-series DMA controller (8 channels, queue/tick/complete, IOC interrupt per channel); SIO serial I/O hub (4 UARTs, 4 SPI buses, 6 I2C buses, 16-pin GPIO mux, peripheral enable + TX counters); SEP Secure Enclave Processor (8-slot key store, KEYGEN/SIGN/VERIFY/WIPE commands, nonce counter, TRNG via LCG). PowerPC: G3/G4 VIA 6522 timer extension (T1 auto-reload, T2 one-shot, GPIO port A/B, shift register, IFR/IER); Cuda MC68HC05 microcontroller (G3/G4: 32-bit RTC, 16-word PRAM, 8-slot ADB event FIFO, power/reset packets); G4 UniNorth U2 northbridge (chipID=0xC0, PCI-A 66MHz AGP/GPU bus, PCI-B 33MHz FW/USB, 2-DIMM memory controller). All QEMU PASS. ~140 HAL seams total. (sigil-kernel 1289352, 3fef9ab, b43039a)

sigilOS HAL batch 19 QEMU PASS — sigilOS HAL batch 19 — QEMU PASS across all 6 seams

apple_dma.sg — M-series DMA Controller (1289352)

The DMA (Direct Memory Access) controller moves data between memory and peripherals without CPU involvement. The M-series DMA is a unified controller serving all on-chip peripherals (ISP, NVMe, USB4, etc.).

8 channels: each channel has independent state (address, count, status). dma_queue(ch, src, dst, len) — queues a transfer on channel ch. Source and destination addresses, plus byte count.
dma_tick(ch) — "executes" one queued transfer: marks it complete, fires the IOC (Interrupt On Completion) interrupt for that channel.
dma_done(ch) — polls the done flag for a channel. Used by polled drivers that don't use interrupts.
IOC interrupt: each channel has an interrupt line. dma_irq_pending(ch) → whether the IOC interrupt is pending. dma_irq_clear(ch) → clear the interrupt. nxfr counter tracks total completed transfers.

Base address: 0x4AD000. PASS: DMA init=1 xfr=1 irq=1

ppc_via.sg — G3/G4 VIA 6522 Timer Extension (1289352)

This commit extends the G3/G4 VIA 6522 with the full timer implementation. The 6522 has two hardware timers (T1 and T2) that drive the system tick and one-shot delays. Extended from earlier VIA seam at 0x495000.

T1 (auto-reload interval timer): via_t1_load(period) sets the timer period. On each via_t1_tick(), T1 counts down. When T1 reaches 0, it fires a T1 interrupt (bit 6 of IFR) and auto-reloads from the latch — it restarts immediately without software intervention. This is the system scheduler tick source.
T2 (one-shot timer): via_t2_load(period) sets a one-shot count. On via_t2_tick(), T2 counts down. When T2 reaches 0, fires a T2 interrupt (bit 5 of IFR) and stops (one-shot, not auto-reload). Used for timeouts and delays.
GPIO port A/B: via_gpio_pa_write(val) / via_gpio_pb_write(val) — write to 8-bit GPIO ports A and B. Read via via_gpio_pa_read() / via_gpio_pb_read(). DDR (data direction registers) control input/output per-pin.
Shift register: via_sr_write(byte) / via_sr_read() — 8-bit serial shift register for bit-bang protocols.
IFR/IER: Interrupt Flag Register (pending) and Interrupt Enable Register (mask). IFR bits: T1=6, T2=5, SR=2, CA1=1, CA2=0. IER writes set or clear masks.

Base address: 0x4AE000. PASS: VIA init=1 tmr=1 sr=1

apple_sio.sg — M-series Serial I/O Hub (3fef9ab)

The SIO is Apple Silicon's multi-protocol serial hub — it consolidates UART, SPI, and I2C controllers plus GPIO mux into a single programmable block. On real M-series hardware, the SIO serves touch controllers, audio codecs, and other low-speed peripherals.

4 UARTs: sio_uart_enable(n) — enable UART 0–3. sio_uart_tx(n, byte) — transmit a byte on UART n. tx_count[n] tracks bytes sent per channel.
4 SPI buses: sio_spi_enable(n) — enable SPI 0–3. sio_spi_xfer(n, tx_byte) — full-duplex transfer (TX one byte, RX one byte). spi_rx_buf[n] holds the last received byte.
6 I2C buses: sio_i2c_enable(n) — enable I2C 0–5 (more than the standalone apple_i2c.sg seam, which is a single-bus controller). sio_i2c_write(bus, addr, val) — write a byte to a device on bus n.
16-pin GPIO mux: sio_gpio_mux(pin, func) — assign one of UART_TX/UART_RX/SPI_SCK/SPI_MOSI/SPI_MISO/I2C_SDA/I2C_SCL/GPIO_OUT to a physical pin (0–15). This is the peripheral pin-mux — the same physical pin can be assigned to different functions.
Peripheral enable register: global enable bits for each subsystem (UART/SPI/I2C independently).

Base address: 0x4AF000. PASS: SIO init=1 bus=1 gpio=1

ppc_cuda.sg — G3/G4 Cuda Microcontroller (3fef9ab)

The Cuda chip is one of the most important chips on G3/G4 Macs — it's a dedicated microcontroller that runs completely independently of the main CPU. It manages the real-time clock, non-volatile parameter RAM (PRAM), ADB routing, power-on/reset sequencing, and low-power "sleep wake" events. Based on the Motorola MC68HC05.

RTC: 32-bit seconds counter (Mac epoch). cuda_rtc_get() → current time. cuda_rtc_set(t) → set time. The Cuda RTC continues running even when the Mac is off (powered by the PRAM battery).
PRAM (Parameter RAM): 16 words of non-volatile storage. Stores boot device, time zone, monitor settings, startup chime, and other persistent preferences. cuda_pram_read(idx) / cuda_pram_write(idx, val).
8-slot ADB event FIFO: ADB events (key presses, mouse movements) from the keyboard/mouse are queued here. cuda_adb_inject(event) → queues an ADB event. cuda_adb_poll() → dequeues the oldest event.
Power/reset packets: cuda_pkt_power() — sends a power-off packet (tells the PMU to cut power). cuda_pkt_reset() — sends a reset packet (restarts the Mac). These are the same commands the OS sends when you choose Shut Down or Restart. npkts counter.

Base address: 0x4B0000. PASS: CUD init=1 rtc=1 adb=1

apple_sep.sg — Secure Enclave Processor (b43039a)

The SEP is Apple's dedicated security coprocessor — completely isolated from the main application processor. It runs its own secure OS, has its own encrypted memory, and handles all cryptographic key operations. The main CPU never sees private key material — it only sends commands and receives verdicts.

8-slot key store: each slot stores a key ID + public key bytes + private key flag. Slots are indexed 0–7.
sep_cmd_keygen(slot) — generates a new key pair in slot slot. Sets the private key flag for the slot, initializes the public key field (deterministic in the HAL model). ngen counter.
sep_cmd_sign(slot, msg) — signs a 4-byte message hash with the private key in slot. Produces a signature (deterministic in the model: msg XOR slot, for verifiability). nsig counter.
sep_cmd_verify(slot, msg, sig) — verifies sig against msg using the public key in slot. Returns 1 on match, 0 on fail. nvfy counter.
sep_cmd_wipe(slot) — destroys the key material in slot. Zeroes the key entry, clears the private key flag. nwipe counter.
Nonce counter: sep_get_nonce() → returns and increments an anti-replay nonce. Used for challenge-response authentication.
TRNG: sep_trng() → returns a pseudo-random 32-bit value (LCG in the model). In hardware, the SEP has a true hardware RNG (thermal noise + conditioning).

sigilOS connection: Touch ID verification and the biometric match cycle (apple_touchid.sg) gate their match verdict through the SEP. The SEP also backs ID_ELEV_TOKEN issuance — the broker calls the SEP for a signed assertion before elevating a capability.

Base address: 0x4B1000. PASS: SEP init=1 key=1 sig=1

ppc_uninorth.sg — G4 UniNorth U2 Northbridge (b43039a)

UniNorth U2 is the northbridge for the Power Mac G4 (AGP) era. It's the central hub that connects the G4 CPU to memory and the two PCI buses (PCI-A for high-speed and PCI-B for standard).

chipID=0xC0: the UniNorth U2 revision identifier, read from the chip ID register.
PCI-A (66 MHz): the high-speed PCI bus — hosts the AGP/GPU slot and (on some G4s) the ATA controller. 66 MHz operation allows the GPU to DMA to system memory at higher bandwidth than standard 33 MHz PCI.
PCI-B (33 MHz): the standard PCI bus — hosts FireWire (IEEE 1394) and USB. 33 MHz is the standard PCI speed.
2-DIMM memory controller: models the G4's dual-DIMM memory slots. uninorth_mem_plug(slot, size_mb) → installs a DIMM in slot 0 or 1. uninorth_mem_total() → total installed memory (sum of both DIMMs). The memory controller arbitrates between CPU and DMA accesses.
uninorth_pci_read(bus, dev, reg) → reads a PCI config register on PCI-A (bus=0) or PCI-B (bus=1).

Base address: 0x4B2000. PASS: UNI init=1 pci=1 mem=1

Batch 19 seam table

Address	Seam	Arch	Commit	PASS
`0x4AD000`	`apple_dma.sg`	Apple Silicon	`1289352`	init=1 xfr=1 irq=1
`0x4AE000`	`ppc_via.sg` (timer ext)	PowerPC G3/G4	`1289352`	init=1 tmr=1 sr=1
`0x4AF000`	`apple_sio.sg`	Apple Silicon	`3fef9ab`	init=1 bus=1 gpio=1
`0x4B0000`	`ppc_cuda.sg`	PowerPC G3/G4	`3fef9ab`	init=1 rtc=1 adb=1
`0x4B1000`	`apple_sep.sg`	Apple Silicon	`b43039a`	init=1 key=1 sig=1
`0x4B2000`	`ppc_uninorth.sg`	PowerPC G4	`b43039a`	init=1 pci=1 mem=1

Batch 19 brings the running total to ~140 HAL seams across Apple Silicon, PowerPC G3/G4, x86, and RISC-V targets. The SEP seam in particular closes a critical security gap: Touch ID and ID_ELEV_TOKEN issuance now have a modeled cryptographic substrate rather than stub returns.