sigil-kernel's seventeenth HAL batch adds 8 more seams. Apple Silicon: M-series RTC (Apple epoch, alarm, 32768Hz monotonic counter, drift trim); Touch ID (SEP-gated biometric: enroll 0–5 fingers, arm/detect/match cycle, anti-spoof counter); MCC (M-series LPDDR5 memory controller: dual-channel 6400MT/s, ECC SECDED, 4-client BW alloc, thermal throttle at 85°C); Apple Neural Engine (ANE: 8 compute tiles, weight DMA, 8-slot dispatch queue). PowerPC: ADB controller (G3/G4: 4-device table, kbd+mouse, TALK reg0, 8-slot event FIFO); FireWire IEEE 1394a (G3/G4: 2-port bus, bus-reset, 8-slot async TX, 8 ISO channels); G5 dual-CPU thermal (2 DigiTemp sensors, 4 PWM fans, T_junction 105°C emergency); Uni-N PCI host bridge (G3/G4: 3-device slot table, pci_scan, VID/DID config read). All QEMU PASS. (sigil-kernel 7ae983d, 30067c1, 664a895, 5c5743a)
1. apple_rtc.sg (7ae983d) — M-series Real-Time Clock
- Apple epoch: Apple Silicon uses a different epoch base than Unix (1970) — the Apple epoch is January 1, 2001 (Mac OS X launch date).
rtc_get_apple()→ seconds since 2001-01-01. rtc_set(ts): set the RTC to a given Apple-epoch timestamp.- Alarm:
rtc_set_alarm(ts)arms a wake alarm.rtc_tick(): each tick checks if the current time ≥ alarm time; if so, fires the alarm and auto-clears (one-shot). - Monotonic counter: 32768Hz source, split into lo (lower 32 bits) + hi (upper 32 bits). Used for high-resolution timekeeping independent of the wall clock.
rtc_mono_lo()+rtc_mono_hi(). - Drift trim:
rtc_trim(trim)adjusts the frequency correction register (for crystal drift compensation). Stored; readable back.
Base address: 0x49C000. PASS: RTC init=1 alm=1 fir=1
2. ppc_adb.sg (7ae983d) — G3/G4 ADB Controller
ADB is the daisy-chain serial bus used on classic Macs (pre-USB) for keyboard and mouse. The G3 and early G4 still carry the ADB controller even with USB present (the built-in keyboard and trackpad went through ADB on these machines).
- 4-device table: each device has an ADB address (default 2=kbd, 3=mouse) and a handler ID.
kbdhandler = 2 (standard ADB keyboard).mousehandler = 4 (ADB mouse with extended protocol). adb_talk(addr, reg): sends a TALK command to the device ataddr, registerreg. Register 0 is the data register (last keycode for kbd, dx/dy for mouse).- 8-slot event FIFO:
adb_inject(addr, data)queues an event.adb_poll()dequeues.ncmd(commands sent) +nevts(events queued) counters.
Base address: 0x49D000. PASS: ADB init=1 dev=1 evs=1
3. apple_touchid.sg (30067c1) — SEP-gated Biometric Seam
Touch ID on Apple Silicon is handled by the SEP (Secure Enclave Processor). The HAL seam models the SEP interface — the main CPU does not see biometric data, only match/no-match verdicts.
- Enroll:
touchid_enroll(finger_id)enrolls a finger (0–5). Up to 6 fingers can be stored. Enrollment is SEP-internal; the HAL only sees the enrollment count. - Match cycle:
touchid_arm()→ sets the sensor active, ready for a scan.touchid_finger_present()→ simulates a finger placement event.touchid_complete()→ returns the verdict:TID_MATCH(enrolled finger) orTID_NOMATCH. - Anti-spoof counter: increments on each NOMATCH, throttles after threshold (prevents brute-force).
- Interrupt flag:
touchid_irq_pending()→ whether a scan result is ready (for interrupt-driven polling).
Base address: 0x49E000. PASS: TID init=1 enr=1 mtc=1
4. ppc_firewire.sg (30067c1) — G3/G4 IEEE 1394a FireWire Controller
- 2-port bus: Port A and Port B. Each can have a device attached.
fw_bus_reset()triggers a bus-reset cycle (required on plug-in).fw_link_on()enables the PHY link layer — necessary before any transaction. - 8-slot async TX queue:
fw_async_send(dest, tcode, data)queues an asynchronous packet (WRITE or READ transaction).tcode= transaction code (WRITE=0x01, READ=0x04). Transactions incrementntxcounter. - 8 ISO channels:
fw_iso_open(ch, bw)claims an isochronous channel with a bandwidth allocation (in 8ns units).fw_iso_tick(ch)simulates one isochronous cycle (1/8000s) for channelch, incrementing the cycle counter. - Cycle counter: 13-bit cycle counter (0–7999, wrapping at 8000 = 1 second). Used for A/V sync on DV cameras and pro audio.
Base address: 0x49F000. PASS: FW1 init=1 lnk=1 iso=1
5. apple_mcc.sg (664a895) — M-series LPDDR5 Memory Channel Controller
- Dual-channel train: Channels A and B each initialized at 6400MT/s.
mcc_train_ch(ch)→ marks channel ready. Both channels must be ready before the controller is operational. - ECC SECDED: Single-Error Correction, Double-Error Detection.
mcc_ecc_enable()enables the ECC engine.ce_counttracks corrected errors (single-bit, not fatal). On a double-bit error, the system enters a fault state. - 4-client BW alloc: The MCC has 4 bandwidth allocation slots (for CPU, GPU, ANE, DMA).
mcc_alloc_bw(client, bw_mbps)sets the BW reservation for each client. Total must not exceed channel capacity. - Thermal throttle:
mcc_thermal_throttle(temp_c)— if temp ≥ 85°C, the MCC drops to a reduced bandwidth mode (throttle state). Clears when temp drops below threshold. Protects the DRAM from overheating.
Base address: 0x4A0000. PASS: MCC init=1 rdy=1 thr=1
6. ppc_thermal.sg (664a895) — G5 Dual-CPU Thermal Management
The Power Mac G5 was notorious for its thermal challenges — it was the first consumer Mac to use liquid cooling (on the high-end dual-2.5GHz). The HAL seam models the G5's Digi-Thermal sensor network and PWM fan controller.
- 2 DigiTemp sensors: CPU A (physical sensor on die) and CPU B (second processor). Each reads a temperature in °C.
- 4 PWM fans (front intake, rear exhaust, CPU A, CPU B): each has a duty cycle (0–255) and a minimum duty (clamp — fans can't be turned off completely).
thermal_set_fan(fan_id, duty)respects the minimum. - Target-based ramp:
thermal_update()compares each sensor against a target temp table. If a CPU is above target, increases the relevant fan duties proportionally. - T_junction emergency: if any sensor reads ≥ 105°C (G5 T_junction limit),
thermal_emg_state=1— triggers an emergency shutdown sequence.
Base address: 0x4A1000. PASS: THM init=1 fan=1 emg=1
7. apple_ane.sg (5c5743a) — Apple Neural Engine
The ANE is Apple's dedicated ML inference accelerator — present on M1 and later. The HAL seam models the ANE's tile-based compute model.
- 8 compute tiles: each tile is an independent inference unit.
ane_load_weights(tile, src, len)→ copies weight data into the tile's local SRAM (simulated as DMA).nwgtcounter tracks weight loads. - 8-slot dispatch queue:
ane_dispatch(tile, input_ptr, output_ptr)queues an inference job on a tile. Jobs are processed in queue order. ane_tick(): processes one queued job per call (fire-and-forget model). Each tick: dequeues the oldest pending job, marks it done, incrementsninfer.- Priority: tiles are processed round-robin. A stalled tile does not block other tiles.
Base address: 0x4A2000. PASS: ANE init=1 wgt=1 inf=1
8. ppc_pci.sg (5c5743a) — G3/G4 Uni-N PCI Host Bridge
- 3-device slot table: models the typical G3/G4 PCI slots (PCI slot 0, 1, 2 — usually ATA, USB, and the AGP bridge on some G3s).
pci_plug_dev(slot, vid, did)inserts a device into a slot (VID=vendor ID, DID=device ID, 16-bit each). pci_cfg_read(slot, offset): reads a PCI config space register. Offset0x00→VID|DID<<16(the standard ID register). Handles unoccupied slots (returns0xFFFF, the PCI "no device" value).pci_cfg_write_cmd(slot, cmd): writes the PCI command register (offset0x04). Used to enable bus-mastering, I/O space, memory space for a device.pci_scan(): enumerates all 3 slots, printing the VID:DID of each present device.ndevcounter. This is what the OS calls on boot to discover PCI devices.
Base address: 0x4A3000. PASS: PCI init=1 scn=1 cfg=1
Batch 17 seam address table
| Address | Seam | Commit | Result |
|---|---|---|---|
0x49C000 | apple_rtc.sg — M-series RTC | 7ae983d | PASS |
0x49D000 | ppc_adb.sg — G3/G4 ADB controller | 7ae983d | PASS |
0x49E000 | apple_touchid.sg — SEP-gated Touch ID | 30067c1 | PASS |
0x49F000 | ppc_firewire.sg — IEEE 1394a FireWire | 30067c1 | PASS |
0x4A0000 | apple_mcc.sg — LPDDR5 MCC | 664a895 | PASS |
0x4A1000 | ppc_thermal.sg — G5 dual-CPU thermal | 664a895 | PASS |
0x4A2000 | apple_ane.sg — Apple Neural Engine | 5c5743a | PASS |
0x4A3000 | ppc_pci.sg — Uni-N PCI host bridge | 5c5743a | PASS |
Batch 17 brings the total to approximately 126 HAL seams across Apple Silicon (M-series) and PowerPC (G3/G4/G5) targets. Each seam is a kernel-level abstraction verified on QEMU before any real-silicon bringup — the seam pattern ensures that the sigilOS kernel can target new hardware without driver-level conditionals scattered through the codebase.