sigil-kernel's sixteenth HAL batch adds 10 more seams — 5 Apple Silicon and 5 PowerPC. Apple: I2C controller (100/400kHz, 4-slave register table, NACK on unknown), AOP coprocessor (Always-On Processor: boot/sleep/wake, 8-slot event FIFO for HEY_SIRI/LID_OPEN/MOTION/NFC_TAP/CRASH/ALS), SMC System Management Controller (16-key table, CPU/GPU temp + fan RPM + backlight, FourCC read/write), USB4/TB4 port controller (Gen2×2=20G / Gen3×2=40G link train, PD 3.1 EPR 140W, DP+TBT3 alt-mode), Apple Silicon PMU (M-series P/E-cluster DVFS 5-OPP, GPU on/off, S0→S3 suspend+wake). PowerPC: GMAC Ethernet (Sun GMAC G4/G5, MDIO auto-neg GbE FD, 8-desc TX+RX ring, cksum offload), VIA 6522 (G3/G4 VIA1+VIA2, RTC bit-bang, 8-byte NVRAM, SCSI+VBLANK IRQ), Symbios 875 UW-SCSI (8-device table, SELECT→CMD→DATA→STATUS→DONE, selection timeout), SWIM3 floppy (MFM 1440K, 80-track seek, r/w sectors, WP guard), G3/G4 PMU coprocessor (battery SoC/V/A/T, RTC get+set, SLEEP/WAKEUP_EVENT). All QEMU PASS. (sigil-kernel f201e7a, 24528ad, 4681230, cf8a563, 2d5534a)
Apple Silicon Seams
apple_i2c.sg — Apple Silicon I2C Controller PASS
Commit f201e7a. MMIO base 0x492000. The Apple Silicon I2C controller drives low-speed peripheral buses — sensors, PMICs, touch controllers, and various platform devices.
- Speeds: 100kHz (standard mode) and 400kHz (fast mode). Speed selection is stored in the controller register and applies to all subsequent transfers.
- 4-slave register table: each slave entry holds an I2C address and up to 8 register slots. The table is seeded at init time from the platform device tree.
i2c_write_reg(addr, reg, val): writes a value to a specific slave register. Returns ACK on a known address+register pair.i2c_read_reg(addr, reg): reads from a slave register into the RX FIFO and returns the value on hit.- NACK: if the address or register is not found in the slave table, returns the NACK code. The caller must retry or fail; the controller does not auto-retry.
PASS: I2C init=1 rw=1 nack=1
apple_aop.sg — Always-On Processor (AOP) Coprocessor PASS
Commit 24528ad. MMIO base 0x494000. The AOP is the low-power coprocessor that stays active while the main CPU cluster is power-gated. It monitors sensors and dispatches wake events without consuming main-cluster power.
- Lifecycle: boot (AOP starts alongside the main CPU) → sleep (AOP stays active while the main CPU is gated) → wake (AOP posts a wake event, main CPU resumes from S3).
- 8-slot event FIFO: events are enqueued by the AOP and drained by the main CPU on wake. Event types:
HEY_SIRI(voice wake word detected),LID_OPEN(clamshell open),MOTION(accelerometer threshold crossing),NFC_TAP,CRASH(motion-pattern crash detection),ALS(ambient light sensor threshold). - Wake counter: increments each time the AOP triggers a main-CPU wake. Used for power accounting.
PASS: AOP init=1 slp=1 wak=1
apple_smc.sg — System Management Controller PASS
Commit 4681230. MMIO base 0x496000. The SMC is the platform telemetry and control hub — the bridge between the OS and thermal, power, and display hardware sensors.
- 16-key register table: keys are 4-byte FourCC identifiers. The seam ships with seeded defaults:
TC0P(CPU die temp, 35°C),TGOP(GPU temp, 42°C),F0Ac(fan 0 actual RPM, 1200),LBKL(backlight level, 50%). smc_read(key): looks up the key in the table and returns the current value.nreadcounter increments.smc_write(key, val): writes a new value to the key entry and returns ACK.nwritecounter increments. Used by the thermal manager to set fan targets and by the display driver to set backlight level.
PASS: SMC init=1 srd=1 swr=1
apple_usb4.sg — USB4 / Thunderbolt 4 Port Controller PASS
Commit cf8a563. MMIO base 0x498000. The USB4/TB4 port controller manages the high-speed port fabric on Apple Silicon Macs — link training, power delivery negotiation, and alternate-mode tunneling.
- Link rates: Gen2×2 (20 Gbps, USB4 Gen2) and Gen3×2 (40 Gbps, USB4 Gen3 / TB4). The controller negotiates the highest rate both ends support during link training. Link-trained flag is set on completion.
- PD 3.1 EPR: Extended Power Range negotiation at 28V / 5A = 140W. The 100W budget register sets the current negotiation ceiling for non-EPR peers that cap at USB PD 3.0.
- Alt modes: DP (DisplayPort tunneled over USB4) and TBT3 (Thunderbolt 3 backward-compatible tunnel). Alt-mode negotiation follows the USB PD alt-mode message sequence.
PASS: U4 init=1 lnk=1 pd=1
apple_pmu.sg — M-Series Apple Silicon PMU PASS
Commit 2d5534a. MMIO base 0x49A000. The M-series PMU drives the DVFS fabric for both CPU clusters and manages the platform power states.
- P-cluster (performance cores): 3500 MHz / 1.15V at max OPP.
- E-cluster (efficiency cores): 2000 MHz / 1.0V at max OPP.
- 5-OPP DVFS table: five operating performance points (frequency + voltage pairs) for each cluster. The PMU selects the active OPP based on a workload governor hint written to the OPP request register.
- GPU power domain: separate on/off gate for the GPU cluster, independent of CPU DVFS.
- Power states: S0 (active, all clusters running) → S3 (suspend: CPU clusters off, RAM retained, AOP active and monitoring) → S5 (power-off).
pmu_sleep()drives the platform to S3;pmu_wake()restores S0. Thewake_srcregister captures the wake event source (from the AOP event FIFO).
PASS: PMU init=1 dvf=1 slp=1
PowerPC Seams
ppc_gmac.sg — G4/G5 GMAC Gigabit Ethernet PASS
Commit f201e7a. MMIO base 0x493000. The Sun GMAC core is the Gigabit Ethernet MAC in G4 and G5 Power Mac systems — a Sun Microsystems IP block licensed into the Apple PowerPC platform.
- MDIO: auto-negotiates GbE full-duplex. PHY link flag is set on negotiation complete. MDIO register read/write for PHY management.
- 8-descriptor TX ring: the caller fills a descriptor (buffer pointer + length) and the MAC transmits.
TXPKTcounter increments per packet sent. - 8-descriptor RX ring: incoming packets are injected by writing descriptors.
RXPKTcounter increments per packet received. DMA fills the caller's buffer. - Checksum offload: hardware TCP/IP checksum computation on TX descriptors — the MAC computes and inserts the checksum, the driver does not need to.
PASS: MAC init=1 lnk=1 pkt=1
ppc_via.sg — G3/G4 VIA 6522 (VIA1 + VIA2) PASS
Commit 24528ad. MMIO base 0x495000. The MOS 6522 Versatile Interface Adapter was the system glue chip in every Apple from the Apple II through the PowerBook G4. The seam models both VIA1 (system VIA) and VIA2 (expansion VIA).
- VIA1 — system VIA: Port A and Port B data registers + DDR (data direction register) for each. RTC bit-bang via serial bit-clock and data lines — the classic Mac RTC protocol over VIA bit manipulation. 8-byte NVRAM store/load via the same bit-bang path (parameter RAM).
- VIA2 — expansion VIA: SCSI IRQ injection (mapped to VIA2 interrupt line) and VBLANK IRQ injection. The IFR (Interrupt Flag Register) accumulates all pending interrupt sources — the kernel interrupt handler reads IFR to dispatch.
PASS: VIA init=1 nvr=1 irq=1
ppc_sym875.sg — G4/G5 Symbios 875 UW-SCSI PASS
Commit 4681230. MMIO base 0x497000. The Symbios Logic SYM53C875 is the Ultra-Wide SCSI controller found in Power Mac G4 and G5 towers.
- 8-device table: each entry holds a SCSI ID, transfer mode (UW = Ultra-Wide 40MB/s, FAST = Fast-20 20MB/s, ASYNC), and a present flag.
- SCSI sequence: SELECT (bus arbitration + target selection) → CMD (command phase, 6/10/12/16-byte CDB) → DATA (data transfer in/out) → STATUS (target sends GOOD or CHECK CONDITION) → DONE (command complete interrupt).
- Selection timeout: if the target SCSI ID is not marked present in the device table, the controller generates a selection timeout interrupt. Correct SCSI behavior for absent targets — the driver must handle this to avoid hanging.
PASS: SCS init=1 cmd=1 sel=1
ppc_swim3.sg — PowerBook G3/G4 SWIM3 Floppy Controller PASS
Commit cf8a563. MMIO base 0x499000. The SWIM3 (Sander-Wozniak Integrated Machine 3) is the final Apple floppy controller, present in PowerBook G3 and G4 models that still shipped with a floppy drive.
- Format: MFM encoding, 1440K (3.5" HD floppy, 80 tracks, 18 sectors/track, 512 bytes/sector). Disk insert and eject events. Motor on/off.
- Seek:
swim3_seek(track)advances or retreats the head to the specified track (0–79). Step direction and count computed from the current position register. - Read sectors:
swim3_read(track, sect)fills the 512-byte sector buffer with the track/sector content. - Write sectors:
swim3_write(track, sect, data)writes 512 bytes to the sector buffer for that track/sector. - Write-protect guard: if the WP flag is set (physical write-protect tab engaged), write operations return an error without touching the sector buffer. No data corruption path.
- CRC proxy: marks each sector as valid or invalid (CRC match simulation for the test harness).
PASS: FD init=1 rds=1 wp=1
ppc_pmu.sg — G3/G4 PMU Coprocessor (CUDA/PMU Chip) PASS
Commit 2d5534a. MMIO base 0x49B000. The G3/G4 PMU is a dedicated coprocessor (the CUDA chip in G3 desktops, the PMU chip in PowerBooks) that manages battery telemetry, the real-time clock, and system power events — the PowerPC equivalent of the Apple Silicon AOP + SMC combined.
- Battery telemetry: SoC (state of charge, 0–100%), voltage (mV), current (mA), temperature (°C), chemistry and status flags. All values readable by the OS for battery gauge display and thermal management.
- RTC:
pmu_rtc_get()returns seconds since the Mac epoch (1904-01-01 00:00:00 UTC — the classic Mac time base).pmu_rtc_set(t)writes a new time value. The PMU RTC runs on a separate coin-cell circuit independent of main power. - Power events:
SLEEPcommand sends the machine to sleep (drives the platform through the power-off sequence).WAKEUP_EVENTcaptures the wake source (lid open, power button, RTC alarm).nslp,nwake, andncmdcounters track activity.
PASS: PPM init=1 bat=1 slp=1
Seam Address Table — Batch 16
| MMIO Base | Seam | Platform | Commit | PASS |
|---|---|---|---|---|
0x492000 |
apple_i2c.sg |
Apple Silicon | f201e7a |
init=1 rw=1 nack=1 |
0x493000 |
ppc_gmac.sg |
PowerPC G4/G5 | f201e7a |
init=1 lnk=1 pkt=1 |
0x494000 |
apple_aop.sg |
Apple Silicon | 24528ad |
init=1 slp=1 wak=1 |
0x495000 |
ppc_via.sg |
PowerPC G3/G4 | 24528ad |
init=1 nvr=1 irq=1 |
0x496000 |
apple_smc.sg |
Apple Silicon | 4681230 |
init=1 srd=1 swr=1 |
0x497000 |
ppc_sym875.sg |
PowerPC G4/G5 | 4681230 |
init=1 cmd=1 sel=1 |
0x498000 |
apple_usb4.sg |
Apple Silicon | cf8a563 |
init=1 lnk=1 pd=1 |
0x499000 |
ppc_swim3.sg |
PowerPC G3/G4 | cf8a563 |
init=1 rds=1 wp=1 |
0x49A000 |
apple_pmu.sg |
Apple Silicon | 2d5534a |
init=1 dvf=1 slp=1 |
0x49B000 |
ppc_pmu.sg |
PowerPC G3/G4 | 2d5534a |
init=1 bat=1 slp=1 |