sigil-kernel's fourteenth HAL batch adds 6 new seams plus an important AGP correction. Apple side: DisplayPort/Thunderbolt/HDMI (HPD, link training lanes/rate/DPCD, 4K144+HDR+VRR+10bpc display caps, MST 4-stream), FaceTime HD ISP (MIPI-CSI2, 1080p/1200p, AE+WB, privacy shutter gate, face-detect relay), MagSafe 3 USB-C PD (28V/5A=140W negotiation, battery SoC/mV/mA/temp/cycles/health, amber/green LED, thermal clamp). PowerPC side: OpenPIC interrupt controller (16 sources, vec/pri/pol/en, TPR masking, IAC+EOI, 4 IPIs), G5 DART IOMMU (32-entry virt→phys, TLB flush, fault record), PowerBook G4 KeyLargo (2×ATA, 2×USB1.1, 64-source IRQ, I2S, WDT). AGP fix: previous ppc_agp commit (029a572) overwrote the pre-existing AGP bridge seam; this commit restores it and moves the new GART-controller model to ppc_agp_ctrl at 0x483000. All QEMU PASS. (sigil-kernel b6c7f33, 827bae4, 110ec12)
apple_displayport.sg — DisplayPort / Thunderbolt / HDMI output
Commit b6c7f33. Address: 0x484000. QEMU: DP init=1 lnk=1 mst=1.
The Apple Silicon display output block covers the full DisplayPort/Thunderbolt/HDMI output path from hot-plug detection through multi-stream transport:
- HPD (Hot-Plug Detect): single flag, set when a display is connected. The kernel polls or waits on HPD before starting link training.
- Link training: lanes (1/2/4), link rate (1.62/2.7/5.4/8.1 Gbps), DPCD (DisplayPort Config Data) result byte. DPCD encodes the outcome of the AUX-channel handshake with the monitor.
- Display capabilities: 4K@144Hz flag, HDR flag, VRR (Variable Refresh Rate) flag, 10bpc (10-bit-per-channel) color flag. All four are independent bits — a display can support any combination.
- MST (Multi-Stream Transport): 4-stream model. Each stream carries a payload ID and a bandwidth allocation (in units of time slots). MST allows one physical DP port to drive up to 4 independent displays via a hub or daisy chain.
apple_facetime_cam.sg — FaceTime HD camera ISP
Commit 827bae4. Address: 0x486000. QEMU: FTC init=1 frm=1 fac=1.
The FaceTime HD seam models the MIPI-CSI2 image signal processor pipeline end-to-end:
- MIPI-CSI2 power: the camera is powered on/off via the ISP power rail — a separate domain from the SoC compute. Power-off cuts the pixel data bus entirely.
- Resolutions: 1080p (1920×1080) and 1200p (1920×1200). Framerates: 30fps and 60fps. The 1200p mode is the taller native sensor resolution used by newer MacBook models.
- Auto-Exposure: exposure time (microseconds) + analog gain (integer multiplier). AE converges over a few frames; the seam exposes the current settled values.
- White Balance: R/G/B gain values (integer×1000 fixed-point). A value of 1000 = unity gain; the ISP adjusts per-channel to reach neutral gray under the ambient light.
- Frame delivery: frame counter increments per capture. Privacy shutter gate: when the privacy shutter flag is set (hardware or software), frame delivery is blocked regardless of ISP power or capture state — the counter does not advance.
- Face detect relay: count (0–N faces) + primary face XY pixel position. This is a lightweight on-ISP detector pass; full ML inference runs separately in userspace.
apple_magsafe.sg — MagSafe 3 USB-C Power Delivery
Commit 110ec12. Address: 0x488000. QEMU: MS init=1 pd=1 bat=1.
The MagSafe 3 seam covers both the USB-C PD negotiation and the battery management controller readout:
- PD negotiation: 28V / 5A = 140W — the MagSafe 3 maximum power contract. The negotiated flag is set once the USB-C PD handshake completes and the adapter agrees to supply 140W.
- Battery monitoring: SoC (State of Charge, 0–100%), voltage mV, current mA (positive = charging, negative = discharging), temperature (°C × 10 fixed-point for 0.1°C resolution), cycle count, and health% (capacity relative to design capacity).
- LED: amber (charging, SoC below 80%), green (charged, SoC at or above 80%), or off (no adapter). The LED state is derived from SoC + negotiated flag.
- Thermal clamp: if battery temperature exceeds the threshold, charging current is clamped to a reduced rate to protect cell chemistry. The clamp flag indicates the reduced-rate state; normal charging resumes once temperature drops.
ppc_openpic.sg — G3/G4/G5 OpenPIC interrupt controller
Commit b6c7f33. Address: 0x485000. QEMU: PIC init=1 irq=1 ipi=1.
OpenPIC is the standard interrupt controller for the G3/G4/G5 PowerPC platform — the PPC equivalent of the x86 8259A PIC. The seam models the full dispatch path:
- 16 interrupt sources (IRQ0–IRQ15). Each source carries: vector (the interrupt number delivered to the CPU), priority (0–15), polarity (active-high or active-low), and enable flag.
- TPR (Task Priority Register): masks all interrupts at or below the current CPU priority level. An IRQ fires only if its configured priority is strictly greater than the current TPR value. TPR is per-CPU in SMP configurations.
- IAC (Interrupt Acknowledge): reading the IAC register returns the highest-priority pending interrupt vector and simultaneously clears that interrupt from the pending set — atomically, so no second IAC can return the same vector.
- EOI (End of Interrupt): written by the interrupt handler when processing is complete. Signals the PIC to re-arm for the next interrupt from that source.
- 4 IPIs (Inter-Processor Interrupts): direct CPU-to-CPU interrupt lines used for SMP coordination (TLB shootdowns, scheduler kicks, etc.).
- Interrupt count accumulator: a monotonic counter per source, incremented on every delivery — useful for diagnostic tools and IRQ load balancing.
ppc_dart.sg — G5 DART IOMMU
Commit 827bae4. Address: 0x487000. QEMU: DRT init=1 map=1 flt=1.
The G5 DART (Direct Access Real-time Translation) is Apple's first IOMMU, introduced with the Power Mac G5 to restrict DMA access from PCI devices:
- 32-entry translation table: each entry maps a virtual DMA address to a physical RAM address.
dart_map(virt, phys)loads a mapping;dart_translate(virt)walks the table to find the physical address. - Enable flag: the DART is inactive until the enable bit is set. Before enable, all DMA addresses pass through untranslated (bypass mode, matching real G5 boot behavior).
- TLB flush counter: incremented on every
dart_flush()call. The flush invalidates all cached translations; the counter lets the kernel audit that flushes are happening at expected points (e.g., after unmapping DMA buffers). - Fault record: if
dart_translate()encounters a miss (no mapping for the requested virtual address), the fault flag is set and the faulting virtual address is latched. No crash — the fault is reported and translation returns 0. The kernel's fault handler can read the record, log it, and decide on action.
ppc_keylargo.sg — PowerBook G4 KeyLargo Mac I/O hub
Commit 110ec12. Address: 0x489000. QEMU: KL init=1 ata=1 usb=1.
KeyLargo is the Mac I/O ASIC on PowerBook G4 and Power Mac G4 systems — the equivalent of a modern PCH, integrating ATA, USB, IRQ routing, audio, and housekeeping onto a single chip:
- 2 ATA channels: ATA33 (primary, for the hard disk) and ATA66 (secondary, for the optical drive). Each channel models the select, drive-ready, and transfer-mode state.
- 2 USB 1.1 ports: each models LS (Low Speed, 1.5 Mbps) and FS (Full Speed, 12 Mbps) connection flags. USB 2.0 was not yet on KeyLargo; that came with KeyLargo's successor, Intrepid.
- 64-source IRQ mask: two 32-bit mask registers covering all 64 KeyLargo interrupt sources. Per-source IRQ inject and IRQ clear operations allow the kernel to drive interrupts from ATA, USB, I2S, and other KeyLargo peripherals.
- I2S audio: enable flag for the I2S serial bus routed to the audio codec (Screamer/Tumbler on G4-era machines). The seam models the bus-enable state; full codec register modeling is a separate seam.
- Watchdog timer: a configurable kick window. If the kernel misses a kick, the WDT reset flag is set — modeling a hardware reset condition that the firmware or supervisor can detect and act on.
AGP seam fix — restoring ppc_agp.sg + new ppc_agp_ctrl.sg
Commit b6c7f33.
HAL batch 12 commit 029a572 introduced ppc_agp.sg as a GART controller model, but it was placed at address 0x427000 — the same address occupied by the pre-existing AGP bridge seam (AGPCMD / AGPSTAT / GART_PTR registers). The new seam silently overwrote the old one, leaving the bridge registers inaccessible.
This commit makes the distinction explicit:
ppc_agp.sgat 0x427000 is restored to its original bridge-register model:AGPCMD(AGP command register, enables AGP mode and sets transfer rate),AGPSTAT(status register, reports AGP capabilities), andGART_PTR(pointer to the GART base address in system RAM).ppc_agp_ctrl.sgat 0x483000 is the new seam for GART-controller internals: GART entry count, FIFO depth, and bandwidth tracking. It uses theAGPCprefix to avoid any future collision with bridge-space names.
No behavioral change for existing software — the two models cover different parts of the AGP specification (bridge config registers vs. GART/FIFO/bandwidth controller). Both seams PASS independently in QEMU.
Batch 14 seam table
| Address | Seam | Commit | QEMU |
|---|---|---|---|
0x484000 | apple_displayport.sg | b6c7f33 | DP init=1 lnk=1 mst=1 |
0x485000 | ppc_openpic.sg | b6c7f33 | PIC init=1 irq=1 ipi=1 |
0x486000 | apple_facetime_cam.sg | 827bae4 | FTC init=1 frm=1 fac=1 |
0x487000 | ppc_dart.sg | 827bae4 | DRT init=1 map=1 flt=1 |
0x488000 | apple_magsafe.sg | 110ec12 | MS init=1 pd=1 bat=1 |
0x489000 | ppc_keylargo.sg | 110ec12 | KL init=1 ata=1 usb=1 |
The AGP seam restoration (ppc_agp.sg at 0x427000, ppc_agp_ctrl.sg at 0x483000) accompanies batch 14 but does not add new addresses — it corrects a collision introduced in batch 12.