Apple Silicon HAL Batch 10: HDMI/DP Audio, PVT Sensors, eFuse, VM Pressure + PPC OFW DT, VIA, SCC, AWACS

sigil-kernel's tenth HAL batch adds 8 more seams — Apple Silicon: HDMI/DP audio sink (4 outputs, 2ch/5.1/7.1 at 48/96kHz, ELD max-ch), PVT (Process/Voltage/Temperature) sensor array (8 sensors, auto-alert on threshold, die temp + VDD rail), eFuse OTP controller (64-word array, secure-boot level, ECID 48-bit, lockdown bits, blow() OTP model), and VM memory pressure notifier (4 levels normal/warning/urgent/critical, free/wired/comp/swap page counters, rising-edge events). PowerPC: OFW flat device tree (32-node DB, root/cpu/memory/pci/chosen, CPU clock-freq + memory range), VIA 6522-compat (PortA/B, T1 16-bit timer, PMU REQ/CUDA bit-bang, SR IFR), SCC Z8530-compat (2 channels modem/printer, BRG, RR0 status, TX+RX async 8N1), AWACS/Screamer/Burgundy audio (WR0/1/3/4/5, stereo 16-bit, vol L/R, mute, mic/line, clip event). All QEMU PASS. (e339a2c, 6a55006, b7466df, 9c1b9ca)

Apple Silicon HAL QEMU batch verification — all 8 seams PASS

Apple Silicon seams

apple_hdmi_audio.sg (e339a2c) — HDMI/DP audio sink

The HDMI/DP audio seam models Apple Silicon's display audio output path: 4 output slots, each with independent channel count (2/6/8), sample rate (48000/96000 Hz), bit width (16/24-bit), and volume. The ELD (EDID-like Data) max-channel field is read from the connected monitor's audio capability descriptor — the kernel queries this to know the highest channel count the sink can accept before committing to a 5.1 or 7.1 stream.

4 output slots; per-slot: channels, rate, width, volume
ELD max-channel field — display audio capability from EDID
Master enable flag, active-output count
Base: 0x460000. PASS: HDMIA init=1 en=1 eld=1

apple_pvt.sg (6a55006) — M1 PVT sensor array

The PVT (Process/Voltage/Temperature) seam exposes M1's on-die sensor array: 8 sensors, each typed as either a die-temperature probe or a VDD rail monitor. pvt_update(id, val) sets the current reading and auto-alerts if the value crosses the per-sensor threshold (rising-edge, increments n_alerts). pvt_clear_alert(id) clears the per-sensor flag and decrements the global counter.

8 sensor slots; per-sensor: type (die-temp / VDD rail), current value, threshold
pvt_update(id, val): auto-alert on threshold crossing
pvt_clear_alert(id): per-sensor alert clear
Die temp (sensor 0) + VDD rail (sensor 1) modeled
Base: 0x462000. PASS: PVT init=1 cfg=1 alr=1

apple_fusectl.sg (b7466df) — eFuse OTP controller

The eFuse seam models Apple Silicon's one-time programmable fuse array: 64 words, each bit settable but never clearable. The array stores the permanent boot configuration for the SoC.

64-word fuse array with real OTP semantics — blow(word, mask) sets bits only
secure-boot level: 0=off, 1=reduced, 2=full (BootROM sign-check enforcement)
ECID: 48-bit chip serial number, split across two fuse words
Lockdown bits: DFU-disable, debug-disable, JEP-production
ADC calibration offset, chip revision, DRAM density
Base: 0x464000. PASS: FUSE init=1 prg=1 dbg=1

Context: The eFuse controller stores the permanent boot configuration. secure-boot-level=2 means BootROM will only boot signed firmware — this is what apple_secboot (the HARD STOP fix) verifies against. The eFuse value is read-once at reset; subsequent writes to the secure-boot field are ignored by the controller.

apple_mem_pressure.sg (9c1b9ca) — VM memory pressure notifier

The memory pressure seam models macOS's VM pressure notification system, which lets the kernel signal userspace when physical memory is under strain. Four levels — NORMAL, WARNING, URGENT, CRITICAL — are computed from live page counters.

4 pressure levels: NORMAL (0) / WARNING (1) / URGENT (2) / CRITICAL (3)
Page counters: free_pages, wired_pages, comp_pages (compressed), swap_pages
mem_pressure_update(free, wired, comp, swap): recalculates level, fires rising-edge event on increase
Configurable thresholds per level; event_count increments on each level-up transition
Base: 0x466000. PASS: MPS init=1 upd=1 evt=1

PowerPC seams

ppc_ofw_dt.sg (e339a2c) — OpenFirmware flat device tree

The OFW device tree seam provides the G3/G4/G5 boot environment's hardware description database. 32 nodes, typed as root, cpu, memory, pci, or chosen. The tree is the primary discovery mechanism for the bootloader and early kernel — no ACPI, no UEFI: OFW is the entire platform description.

32-node DB; node types: root, cpu, memory, pci, chosen
ofw_alloc(type), ofw_set_data(node, ptr, len), ofw_find_by_type(type)
CPU data fields: clock-freq (word0) + cache-size (word1); memory: base + size range
Base: 0x461000. PASS: OFDT init=1 all=1 fnd=1

ppc_via.sg (6a55006) — G3/G4 VIA 6522-compat

The VIA seam models the 6522 Versatile Interface Adapter used in G3/G4 Macs as the PMU communication bridge and general-purpose I/O controller. The real VIA is how the CPU talks to the Cuda or PMU chip for power management, ADB (Apple Desktop Bus), and RTC.

PortA/B with DDRA/B (data-direction registers)
T1 16-bit timer: latch + countdown
IFR/IER (interrupt flag/enable registers)
PMU REQ bit6 (request line to Cuda/PMU); CUDA bit-bang model
SR write with IFR-SR flag assertion
Base: 0x463000. PASS: VIA init=1 pmu=1 sr=1

ppc_scc.sg (b7466df) — G3/G4 SCC Z8530-compat

The SCC seam models the Zilog Z8530 Serial Communications Controller, which provided modem and printer serial ports on G3/G4 Macs. Two independent full-duplex channels, each with its own baud rate generator.

2 channels: modem (CHA) and printer (CHB)
WRx configuration registers; BRG time-constant for baud rate
RR0 status: TX-empty, RX-available, DCD (carrier detect), CTS
TX byte + RX inject/read; async 8N1 model
Base: 0x465000. PASS: SCC init=1 cfg=1 rxt=1

ppc_awacs.sg (9c1b9ca) — G3 AWACS/Screamer/Burgundy audio codec

The AWACS seam covers the G3/G4 audio DAC family — AWACS, Screamer, and Burgundy were successive revisions of the same codec architecture used across iMac G3, PowerMac G3, and PowerMac G4. The seam covers all three via a unified register model.

Control regs: WR0/WR1/WR3/WR4/WR5 (codec config); BRG TC (bit clock); RR0/RR1/RR8 (status)
Stereo 16-bit PCM; volume L/R independent; mute flag
Input select: mic / line-in
Clip event status: LOCK + CLIP bits; TX/RX byte counters
Base: 0x467000. PASS: AWACS init=1 vol=1 clp=1

Note: The G3 iMac and PowerMac G3/G4 used AWACS, Screamer, and Burgundy as successive revisions of the same DAC family. The seam covers all three via the same register model — hardware differences are in the codec ID field, not the control interface.

HAL milestone: ~80 components

With batch 10 complete, the sigil-kernel HAL now covers ~80 components across both Apple Silicon and PowerPC G3/G4/G5. Every major subsystem needed for a functional OS bring-up on either architecture is modeled:

CPU + MMU + cache

AArch64 + G3/G4/G5 PPC; TLB, cache ops, exception vectors, privilege levels

Interrupts + DMA + timers

AIC/GIC + OpenPIC; DART/IOMMU; system timer + VIA T1 + architected timer

Serial + audio + storage

UART/SCC; HDMI audio + AWACS/Screamer; NVMe + IDE + USB mass storage

Network + display + power

Ethernet + WiFi stubs; GPU framebuffer + HDMI; PMIC + PVT sensors + eFuse

Security + platform

Secure boot + eFuse OTP + memory pressure; OFW DT + VIA PMU + CUDA bit-bang

The seam layer is ready for real-silicon integration. Component files need no changes — only the hardware loopback stubs at the seam boundary are replaced with real MMIO accessors when running on physical hardware.